SCTL using same clock
I am using 2 SCTL with the same clock, are they running in parallel or sequential?
Details:
I am using the 1st SCTL to acquire ADC data. It is triggered by a button. During the acquisition, when the 1st SCTL detects an event, it sends a FIFO message to start another SCTL, which should run at the same speed. So I programmed another SCTL using the same ADC clock as the timer.
But I found the behavior looks strange. I don't know if these 2nd SCTL is running after the 1st is stopped.
Hi
Parallel loops run in parallel. Since these are both SCTL I can guarantee that there are no shared resources and each loop should behave completely independent of the other. What exactly is the "strange" behavior?
Just guessing, there are multiple cycles of latency between FIFOs. Meaning if I write to a FIFO on the first iteration that data may not be available to read from the FIFO until up to 6 clock cycles in this case. You need to monitor the empty and full flags to validate his data.
Can send some screenshots of your code and explain the strange behavior in a little more detail?
Thanks
Jerry
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LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
Hello NI forums,
Question:
See the attached picture from a modified version of the LabVIEW DRAM FIFO example. It probably explains my question more effectively than the paragraphs below.
What is the difference to the LabVIEW / Xilinx compiliers, if any, between placing two independent branches of code in the same SCTL, versus placing them in individual SCTLs (in the same clock domain)?
Misc. comments:
I have briefly experimented with this concept using the included LabVIEW DRAM FIFO example (example finder >> Hardware Input and Output >> FlexRIO >> External Memory >> Simple External Memory FIFO.lvproj).
I compiled the default example (the read and write interfaces are in separate 40MHz SCTLs) five separate times. Then I put the read and write interfaces in the same 40MHz SCTL and compiled another five times. The result (when both read and write interfaces were in the same SCTL) was a reduction in resource usage (according to the compilation summary).
However, due to my lack of knowledge I'm hesitant to conclude that placing everything in one SCTL is always the best option. For example, I do not know what is created 'behind the scenes' with each SCTL. Perhaps putting independent branches of code in separate SCTLs makes it possible to route clock, reset, implicit enable, etc. signals more effectively.
Background information:
My task involves acquiring 2 channels of analog data using the NI 5772 and PXIe-7966. Data acquisition takes place in a 200MHz SCTL, and downstream processing is performed in a 100MHz SCTL.
During a vast majority of the 100MHz SCTL processing stages of the FPGA VI, the 2 channels of data do not interact with eachother. So it would be easy for me to place them in separate 100MHz loops if doing so would somehow help the design (timing, resource usage, etc.).
Thanks!
Attachments:
question.png 76 KBIntaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
10-28-2014 12:11 PM
Just out of interest, what is the resource usage differential between the two versions?
In response to the above comment,
This is a little embarrassing, but it seems like the resource usage is similar than I initially thought for this particular example. I think the previous compilations that I based my assumption on coincidentally used more resources in the 2-SCTL loop case. I just compiled each version two additional times (see below).
Here's the version with everything in one loop:
Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Here's the version with the read and write in separate loops:
Device Utilization
Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4852 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 19.4% (2859 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4859 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244) -
How can I use external clock to implement a delay?
Hi all,
I am testing to use external clock to drive dev/PFI0 (on device 6711) which is used as the clock for the analog ouput. I have thinking two applications by using the external clock but I don't have much idea on the implementation yet.
First of all, I have a sequence of data (array) with each sample being sent at the interval of 1us. I use an external clock (10MHz) driving the PFI0 so it is pretty easy to achieve that goal. I am thinking what happen if I want each sampel being sent at different time. For example, if I have 5 samples, I want the first one sent 1us after the task start and wait 2us to send the 2nd sample, wait 5us to send the 3rd sample and wait 11 us to send the 4th sample, and wait 1us to send the last sample. Is it possible to achieve that based on the external clock?
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To answer your first question, yes you could send data in that fashion. You would have to programmatically build a pulse train and use that to trigger the sending of data. The answer to the second question is essentially the same. You should be able to programmatically build a pulse train with a delay and use it as trigger to begin whatever operation you have.
Jonathan L.
Applications Engineer
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Using External Clock to write counter value to buffer
Using CTR mode config which input controls at what frequency the counter value gets written to the buffer? How do I set it up so the counter value is written to the buffer at the same time Anologue inputs are written to a buffer, without using the other counter.
Hello,
Could you please explain what type of counter operation are you interested in doing? That would help me in suggesting something.
But if I roughly understand what you are saying here, you can use a same clock to provide as scan clock for analog input and then use that clock for the counter. But depending on what counter operation you are trying to do will decide whether that clock be provided as source or Gate.
You may take a look at examples provided at the following location too :
Measurement Hardware
Sincerely
Sastry V
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http://support.apple.com/kb/ht5661
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Can we use same program ID for more than one RFC scenarios
Hi experts,
I am working on a RFC to FILE scenario. I have created one TCP/IP connection in SM59 with a program ID. Can we use this program ID for more than one scenario. I have written code as below
data: iquote type standard table of ZIQMD initial size 0,
IPRODUCT type standard table of ZPMS initial size 0,
wa_quote type ZIQMD,
wa_PRODUCT type ZPMS.
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Thanks in advance.
Thanks & Regards,
Poorna.Just tried this and I can confirm that my earlier understanding was correct!
One of my colleagues confused me out and the conclusion is,
1. You need a separate TCP IP Connection for every interface with a Unique program ID.
Regards
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How to update software on multiple iPhones using same iTunes account?
SeanB15 wrote:
Here are more details on my situation which should help clarify things...
I purchased three iPhone 4 models back when they first came out (for my family) that all share the same iTunes account for access to apps and music, but each phone/user still has his/her custom contact list, email accts, and select lists of apps and music from the one iTunes acct library. The problem is (as I understand it) that I can only update the software on one of the three iPhones – the primary phone I used to setup the iTunes acct without wiping out the separate contact lists, etc. As it stands today... the first (primary) iPhone associated with the iTune acct has been updated with the latest software version 5.1.1 and sync'd up with all the apps, music, etc from the one iTune acct, while the other two iPhones are still running on the original software version 4.0.2 and are experiencing problems now. I was advised by AT&T back in January that it would be necessary to setup separate iTunes accts for the second and third iPhones in order to receive system updates and still be able to manage separate contact lists, etc. If I go this route, I assume we will lose all the apps on phones #2 and #3 that we have been "sharing"... correct? Since this AT&T advice was prior to iCloud coming out, would iCloud be a better solution or at least part of the solution? I really don't yet understand how iCloud works. Hopefully, one of you can help me??
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