Sending an Image file via UART

Question

Hi All,
1. Is it possible to send an image file( .jpg -1080p) from PC to FPGA(ML605 evaluation board) via UART ?
2. .jpg to .hex to .txt then  through hyper terminal ? or any  other way ?
Meganadhan
 

Answer 1

thanks ignacio
i will try it letter
but for sending an image to fpga, can i use realterm?  actually i'm doing image encryption project and the size pixel is 1600X1600, it's very big , but it's ok if it will take a long time for transfer it via UART because i just want to make sure that my alghorithm was true.
 and i have some trouble with the uart rx code. i would like to simulate it with random bit that represent transfer bit from pc, but it's hard to sychronise the timing between uart rx and the random bit program , here the code
RANDOM BIT
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity random is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
Port ( clk :in STD_LOGIC;
output : out STD_LOGIC);
end random;
architecture Behavioral of random is
signal counter: integer:=0;
begin
process (clk)
begin
if rising_edge(clk) then
counter <= counter+1;
if counter= (g_CLKS_PER_BIT-1) then
output <= '1';
elsif counter=55 then
output <= '0';
elsif counter=65 then
output <= '0';
elsif counter=75 then
output <= '0';
elsif counter=85 then
output <= '1';
elsif counter=95 then
output <= '0';
elsif counter=105 then
output <= '0';
elsif counter=115 then
output <= '0';
--elsif counter =1 then
counter <= 0;
end if;
end if;
end process;
end Behavioral;
----------------------------------------------------------------------UART RX
-- File Downloaded from http://www.nandland.com
-- This file contains the UART Receiver. This receiver is able to
-- receive 8 bits of serial data, one start bit, one stop bit,
-- and no parity bit. When receive is complete o_rx_dv will be
-- driven high for one clock cycle.
-- Set Generic g_CLKS_PER_BIT as follows:
-- g_CLKS_PER_BIT = (Frequency of i_clk)/(Frequency of UART)
-- Example: 10 MHz Clock, 115200 baud UART
-- (10000000)/(115200) = 87
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
entity receive is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
port (
i_clk : in std_logic;
i_rx_serial : in std_logic;
o_rx_dv : out std_logic;
o_rx_byte : out std_logic_vector(7 downto 0)
end receive;
architecture rtl of receive is
type t_SM_MAIN is (s_IDLE, s_RX_START_BIT, s_RX_DATA_BITS,
s_RX_STOP_BIT, s_CLEANUP);
signal r_SM_MAIN : t_SM_MAIN := s_IDLE;
signal r_RX_DATA_R : std_logic := '0';
signal r_RX_DATA &colon; std_logic := '0';
signal r_CLK_COUNT : integer range 0 to g_CLKS_PER_BIT-1 := 0;
signal r_BIT_INDEX : integer range 0 to 7 := 0; -- 8 Bits Total
signal r_RX_BYTE : std_logic_vector(7 downto 0):= (others => '0');
signal r_RX_DV : std_logic := '0';
begin
-- Purpose: Double-register the incoming data.
-- This allows it to be used in the UART RX Clock Domain.
-- (It removes problems caused by metastabiliy)
p_SAMPLE : process (i_clk)
begin
if rising_edge(i_clk) then
r_RX_DATA_R <= i_rx_serial;
r_RX_DATA <= r_RX_DATA_R;
end if;
end process p_SAMPLE;
-- Purpose: Control RX state machine
p_UART_RX : process (i_clk)
begin
if rising_edge(i_clk) then
case r_SM_MAIN is
when s_IDLE =>
r_RX_DV <= '0';
r_CLK_COUNT <= 0;
r_BIT_INDEX <= 0;
if r_RX_DATA = '0' then -- Start bit detected
r_SM_MAIN <= s_RX_START_BIT;
else
r_SM_MAIN <= s_IDLE;
end if;
-- Check middle of start bit to make sure it's still low
when s_RX_START_BIT =>
if r_CLK_COUNT = (g_CLKS_PER_BIT-1)/2 then
if r_RX_DATA = '0' then
r_CLK_COUNT <= 0; -- reset counter since we found the middle
r_SM_MAIN <= s_RX_DATA_BITS;
else
r_SM_MAIN <= s_IDLE;
end if;
else
r_CLK_COUNT <= r_CLK_COUNT + 1;
r_SM_MAIN <= s_RX_START_BIT;
end if;
-- Wait g_CLKS_PER_BIT-1 clock cycles to sample serial data
when s_RX_DATA_BITS =>
if r_CLK_COUNT < g_CLKS_PER_BIT-1 then
r_CLK_COUNT <= r_CLK_COUNT + 1;
r_SM_MAIN <= s_RX_DATA_BITS;
else
r_CLK_COUNT <= 0;
r_RX_BYTE(r_BIT_INDEX) <= r_RX_DATA;
-- Check if we have sent out all bits
if r_BIT_INDEX < 7 then
r_BIT_INDEX <= r_BIT_INDEX + 1;
r_SM_MAIN <= s_RX_DATA_BITS;
else
r_BIT_INDEX <= 0;
r_SM_MAIN <= s_RX_STOP_BIT;
end if;
end if;
-- Receive Stop bit. Stop bit = 1
when s_RX_STOP_BIT =>
-- Wait g_CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if r_CLK_COUNT < g_CLKS_PER_BIT-1 then
r_CLK_COUNT <= r_CLK_COUNT + 1;
r_SM_MAIN <= s_RX_STOP_BIT;
else
r_RX_DV <= '1';
r_CLK_COUNT <= 0;
r_SM_MAIN <= s_CLEANUP;
end if;
-- Stay here 1 clock
when s_CLEANUP =>
r_SM_MAIN <= s_IDLE;
r_RX_DV <= '0';
when others =>
r_SM_MAIN <= s_IDLE;
end case;
end if;
end process p_UART_RX;
o_rx_dv <= r_RX_DV;
o_rx_byte <= r_RX_BYTE;
end rtl;
TOP
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
port(cl_k: in std_logic
end top;
architecture Behavioral of top is
--component random
component random is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
Port ( clk :in STD_LOGIC;
output : out STD_LOGIC
end component;
--component uart rx
component receive is
generic (
g_CLKS_PER_BIT : integer := 87 -- Needs to be set correctly--> 10 MHZ/115200(baud rate)
port (
i_clk : in std_logic;
i_rx_serial : in std_logic;
o_rx_dv : out std_logic;
o_rx_byte : out std_logic_vector(7 downto 0)
end component;
--signal
signal mlebu:std_logic;
signal enabl:std_logic;
signal metu :std_logic_vector (7 downto 0);
begin
a:random port map( output=>mlebu,
clk=>cl_k
b:receive port map( i_clk=>cl_k,
i_rx_serial=>mlebu,
o_rx_dv=>enabl,
o_rx_byte=>metu
end Behavioral;
regards
halim