Share exporting...done..but showing time remaining

I shared a short video clip, sending it to DVD. It worked just fine, creating a short, plain jane dvd. The next morning I saw that FCP had a dialog box saying "Exporting 2 Output Files: Finished Disc 100% complete". and the grey barber pole was just continuing along. I'm not worried about it but just curious. Is this normal? One would expect it to disappear when all was done or ask if you wanted to share/burn another copy or something.

dreamer_tooms, welcome to the forum,
if you have the AC adapter attached it will only show %age charge level; remaining time is not a factor when AC is attached.
When running on battery you can right click the battery guage and choose between time and %age charge level, just left click which it should display.
Hope this helps
Andy ______________________________________
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PAR done but shows PAR Error on planahead 14.7

hi,
am getting PAR error while in log it shows PAR done!!!
this happens only when i change the reset pin of my design from V5 to any other pin.
my design consists of microblaze also.
Thanks

following is the logi file
*** Running ngdbuild
with args -intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc "top_module.ucf" -bm "top_module.bmm" "top_module.edf"
Command Line:
D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc top_module.ucf -bm top_module.bmm
top_module.edf
Executing edif2ngd -quiet "top_module.edf" "_ngo\top_module.ngo"
Release 14.7 - edif2ngd P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading NGO file
"D:/BEL_DRC/BEL_DRC/mohammad_ADC_july24/spartan6_adc2.runs/impl_1/_ngo/top_modul
e.ngo" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "top_module.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Processing BMM file "top_module.bmm" ...
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Perform
ance.Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst' has unconnected
output pin
Partition Implementation Status
No Partitions were found in this design.
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Writing NGD file "top_module.ngd" ...
Total REAL time to NGDBUILD completion: 37 sec
Total CPU time to NGDBUILD completion: 9 sec
Writing NGDBUILD log file "top_module.bld"...
NGDBUILD done.
*** Running map
with args -intstyle pa -w "top_module.ngd"
Using target part "6slx45fgg484-2".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 17 secs
Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:1f7146f2) REAL time: 19 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:1f7146f2) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:c84c17d2) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:fb9deab) REAL time: 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:fb9deab) REAL time: 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:fb9deab) REAL time: 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
Phase 9.8 Global Placement
Phase 9.8 Global Placement (Checksum:fe784d) REAL time: 53 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:fe784d) REAL time: 53 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 3 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 4 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:ee3892b6) REAL time: 1 mins 4 secs
Total REAL time to Placer completion: 1 mins 13 secs
Total CPU time to Placer completion: 1 mins 9 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 19
Slice Logic Utilization:
Number of Slice Registers: 2,768 out of 54,576 5%
Number used as Flip Flops: 2,761
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,495 out of 27,288 9%
Number used as logic: 2,244 out of 27,288 8%
Number using O6 output only: 1,810
Number using O5 output only: 48
Number using O5 and O6: 386
Number used as ROM: 0
Number used as Memory: 157 out of 6,408 2%
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 93
Number using O6 output only: 26
Number using O5 output only: 1
Number using O5 and O6: 66
Number used exclusively as route-thrus: 94
Number with same-slice register load: 90
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,309 out of 6,822 19%
Number of MUXCYs used: 228 out of 13,644 1%
Number of LUT Flip Flop pairs used: 3,563
Number with an unused Flip Flop: 1,031 out of 3,563 28%
Number with an unused LUT: 1,068 out of 3,563 29%
Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
Number of unique control sets: 256
Number of slice register sites lost
to control set restrictions: 1,096 out of 54,576 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 316 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 32 out of 116 27%
Number of RAMB8BWERs: 8 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 14 out of 16 87%
Number used as BUFGs: 14
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 5 out of 8 62%
Number used as DCMs: 5
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.63
Peak Memory Usage: 536 MB
Total REAL time to MAP completion: 1 mins 18 secs
Total CPU time to MAP completion: 1 mins 14 secs
Mapping completed.
See MAP report file "top_module.mrp" for details.
*** Running par
with args -intstyle pa "top_module.ncd" -w "top_module_routed.ncd"
Constraints file: top_module.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment
D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\.
"top_module" is an NCD, version 3.2, device xc6slx45, package fgg484, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 2,768 out of 54,576 5%
Number used as Flip Flops: 2,761
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,495 out of 27,288 9%
Number used as logic: 2,244 out of 27,288 8%
Number using O6 output only: 1,810
Number using O5 output only: 48
Number using O5 and O6: 386
Number used as ROM: 0
Number used as Memory: 157 out of 6,408 2%
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 93
Number using O6 output only: 26
Number using O5 output only: 1
Number using O5 and O6: 66
Number used exclusively as route-thrus: 94
Number with same-slice register load: 90
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,309 out of 6,822 19%
Number of MUXCYs used: 228 out of 13,644 1%
Number of LUT Flip Flop pairs used: 3,563
Number with an unused Flip Flop: 1,031 out of 3,563 28%
Number with an unused LUT: 1,068 out of 3,563 29%
Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 316 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 32 out of 116 27%
Number of RAMB8BWERs: 8 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 14 out of 16 87%
Number used as BUFGs: 14
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 5 out of 8 62%
Number used as DCMs: 5
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): Standard
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 8 secs
WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[31] has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[30] has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 20567 unrouted; REAL time: 9 secs
Phase 2 : 15210 unrouted; REAL time: 13 secs
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[0].clk_wizard_inst/dcm_sp_inst/CLKIN
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[2].clk_wizard_inst/dcm_sp_inst/CLKIN
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[3].clk_wizard_inst/dcm_sp_inst/CLKIN
Phase 3 : 5729 unrouted; REAL time: 33 secs
Phase 4 : 5729 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 35 secs
Updating file: top_module_routed.ncd with current fully routed design.
Phase 5 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 6 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 7 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 8 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 9 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 10 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 50 secs
Total REAL time to Router completion: 50 secs
Total CPU time to Router completion: 50 secs
Partition Implementation Status
No Partitions were found in this design.
Generating "PAR" statistics.
Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
| inst/clk_50_0000MHz | BUFGMUX_X2Y10| No | 960 | 0.064 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[0] | BUFGMUX_X2Y9| No | 28 | 0.057 | 1.766 |
+---------------------+--------------+------+------+------------+-------------+
| clk_rd_sig | BUFGMUX_X2Y4| No | 104 | 0.052 | 1.770 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[1] | BUFGMUX_X2Y11| No | 28 | 0.028 | 1.743 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[2] | BUFGMUX_X2Y1| No | 27 | 0.031 | 1.771 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[3] | BUFGMUX_X3Y8| No | 27 | 0.028 | 1.739 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
|inst/microblaze_0_md | | | | | |
| m_bus_Dbg_Clk | BUFGMUX_X3Y13| No | 61 | 0.055 | 1.767 |
+---------------------+--------------+------+------+------------+-------------+
| clk_counter_sig | BUFGMUX_X2Y2| No | 2 | 0.002 | 1.738 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[1] | BUFGMUX_X3Y5| No | 2 | 0.000 | 1.770 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[0] | BUFGMUX_X3Y15| No | 7 | 0.045 | 1.767 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[3] | BUFGMUX_X3Y16| No | 2 | 0.000 | 1.722 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[2] | BUFGMUX_X2Y12| No | 2 | 0.000 | 1.766 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk270 | | | | | |
| _sig[0] | BUFGMUX_X3Y14| No | 4 | 0.022 | 1.765 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
|inst/microblaze_0_md | | | | | |
| m_bus_Dbg_Update | Local| | 20 | 4.177 | 6.233 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
TS_test_module_inst_mb_inst_clock_generat | SETUP | 7.791ns| 12.209ns| 0| 0
or_0_clock_generator_0_SIG_PLL0_CLKOUT0 | HOLD | 0.240ns| | 0| 0
= PERIOD TIMEGRP "test_mod | | | | |
ule_inst_mb_inst_clock_generator_0_clock_ | | | | |
generator_0_SIG_PLL0_CLKOUT0" TS_ | | | | |
sys_clk_pin HIGH 50% | | | | |
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
pin" 50 MHz HIGH 50% | | | | |
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin | 20.000ns| 5.000ns| 12.209ns| 0| 0| 0| 358509|
| TS_test_module_inst_mb_inst_cl| 20.000ns| 12.209ns| N/A| 0| 0| 358509| 0|
| ock_generator_0_clock_generato| | | | | | | |
| r_0_SIG_PLL0_CLKOUT0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
1 signals are not completely routed. See the top_module_routed.unroutes file for a list of all unrouted signals.
WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
completely routed in this design. See the "top_module_routed.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNING:Par:283 - There are 18 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 53 secs
Total CPU time to PAR completion: 52 secs
Peak Memory Usage: 515 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 23
Number of info messages: 0
Writing design to file top_module_routed.ncd
PAR done!

Show time remaining on alarmclock when it is set

Hello. Sorry in advance if this is the wrong part of the forums to post this.
I would just like to suggest a feature that I had on my old phone and that I am now missing on my Iphone 6.
When I set the alarm to wake me up at some point in the future it would be nice if the phone told me how long time there was till the alarm activates.
If i set it to 20.15 at 18.00 then it would be nice to see alarm in 2 hours and 15 minutes.
I hope this will be implemented soon.

Sounds like a goo idea but you are not talking to Apple here only other users.
You use use the Apple feedback forms Apple - Feedback to suggest this directly to Apple.

Podcast iphone app - today, slider showed time remaining and now it disappeared. WTH!?

I researched this issue on the Discussion board last night, and saw things were missing from my screen. Miraculously, this a.m., INDEED the slider and a Speed button were now visible on my Podcast app on my iPhone 4. NOW, these items have disappeared again! They are showing on the Music app. What happened ???

Found the answer!! Tap the top 1/3 of the screen and the timer, speed and Timer buttons all appear!!! Hope it helps someone else.

Interface execution done(but showing some error in Operator on seeing execution)

Hi Folks,
There is the following error coming while execution of interface.
ODI-1217: Session INT_INFext_RT_FF (20001) fails with return code 30088.
ODI-1226: Step INT_INFext_RT_FF fails after 1 attempt(s).
ODI-1240: Flow INT_INFext_RT_FF fails while performing a Loading operation. This flow loads target table TRG_SALES_PERSON.
ODI-1228: Task SrcSet0 (Loading) fails on the target ORACLE connection ODI_STAGE.
Caused By: java.sql.SQLException: ORA-30088: datetime/interval precision is out of range
at oracle.jdbc.driver.T4CTTIoer.processError(T4CTTIoer.java:462)
at oracle.jdbc.driver.T4CTTIoer.processError(T4CTTIoer.java:405)
Regards
Rachin Gupta

Sorry for the delay. See document 741294.1 in support system. Based on the document this is generally caused by Incorrect mapping between columns or Incorrect datatype conversion specification. To resolve:
Verify the Column attributes of target table
Verify the Column Converted to tab
Verify the Converted from tab
Jani Rautiainen
Fusion Applications Developer Relations
https://blogs.oracle.com/fadevrel/

I have restored my iphone and its saying time remaining is about 24 hours can you please help. can i switch the phone back on ? please help ??? :(

after there being an error in trying to update the software it said i have to restore my phone which i have done but says time remaining is about 24 hours . can you please help ? i just want to switch my phone on again .

Hello lyndsey1430,
From what I can gather, it sounds like you're having issues restoring your device. After reviewing your post, I have located an article that can help in this situation. It contains helpful advice concerning recovery mode:
If you can't update or restore your iPhone, iPad, or iPod touch
Use recovery mode
You might need to use recovery mode to restore your device in these cases:
iTunes doesn't recognize your device or says it's in recovery mode.
You see the Apple logo onscreen for several minutes with no progress bar.
You see the Connect to iTunes screen.
Learn what to do if you see the progress bar onscreen for several minutes.
To put your device into recovery mode, follow these steps:
Turn off your device and leave it off.
Plug in your device's USB cable to a computer with iTunes.
Hold down the Home button on your device as you connect the USB cable. Keep holding down the Home button until you see the Connect to iTunes screen.
When you see this screen, release the Home button. If you don't see this screen, try steps 1 through 3 again.
When your device is connected, iTunes will open. You'll see a message saying that iTunes has detected an iPhone, iPad, or iPod touch in recovery mode.
Use iTunes to restore your device. Restoring in recovery mode will erase your device. If you previously synced with iTunes or iCloud, you might be able to restore from your backup.
Get more help
Learn what to do if you don't see your device in iTunes for OS X, or in iTunes for Windows.
If you put your device into recovery mode by mistake, restart it. Or you can wait 15 minutes and your device will exit recovery mode by itself.
Thank you for contributing to Apple Support Communities.
Cheers,
BobbyD

HP G62 battery - time remaining never shown

Hi,
I have an HP G62 and am very pleased with it. However, there is one little annoyance in that in Windows 7, the battery percentage is always shown but never with an amount of time remaining. I also use Ubuntu, and the problem presents itself in more ways there:
The time remaining is never shown but the percentage is
In Gnome Power management, a 'rate' or 'voltage' is never shown - ie it's always zero
The 'Energy when full' and 'Energy (design)' figures change every reboot.
I read somewhere that a BIOS update may sort this issue but I've upgraded to F46 and still no progress. I've also done a full calibration of the battery and still it seems no operating system can read a discharge rate for the battery.
Other people have reported this as a bug in Ubuntu https://bugs.launchpad.net/ubuntu/+source/gnome-power-manager/+bug/661759 but I think it's more a hardware fault. Has anyone else experienced the issue and does anyone know of a fix?

I have an sd card and a cf card running ubuntu 10.10 on an external card reader. On an nc4400 and a tc4400 everything reads as it should in the power manager. The battery indicator at the top shows time remaining and the design capacity always stays the same.
I think a lot of the problem is in the bios in that it's the bios that allows the os to see the sensors. Over the years computer manufacturers have taken out a lot of options in the bios. I think that they think that we are too dumb to choose the right settings in the bios and that we cause a lot of warranty problems by changing settings in the bios. For instance virtualization.
That's kinda why I stay with the older machines, I like being able to change my settings. Plus, there's not a whole lot of modded bios out there for hp's because hp locks their bios down pretty tight. That's why we can't get a fan control to work like you can for thinkpads. I don't have any solutions for you but I do feel your pain. I would love to get a new machine, but I just don't trust them.
I don't think it's any kind of hardware problem though. I really think it's in the bios. You might try going on MyDigitalLife and poking around there, that would be the place to find a modded bios if there was one. Or maybe another solution.
Did someone help you? Pay it forward. Help someone else.
NC4400, TC4400 Win 7 Ultimate, xp pro, both dual boot
a bunch of thinkpads

Word I convert a PDF to WORD format. I have signed up to Export PDF but everytime I try to covert all it asks is that I sign in again and I cant get past it.

convert a PDF to WORD format. I have signed up to Export PDF but every time I try to covert all it asks is that I sign in again and I cant get past ti and the covert button is not available.anyone else having this problem or know how to fix it.

Hi bouerbird,
I just l looked at your account using the same email address that you use here in the forums, and don't see any order history for you. Is it possible that you signed up using a different email address?
Best,
Sara

SRM error 'process time remaining' for Rfx

The simultaneous opening of the RFxs were performed. But it was not possible to open the offers as the system was showing ' process time remaining'. At that time the times remaining for the 3 RFxs was shown around 4 hours 30 minutes. The offers were tried to open next day. Again the system was showing ' process time remaining', but the time remaining for the 3 RFxs are shown about 2 hours .Please suggest .

Hi Srvinivas,
The following documents may be of some help to you:
http://help.sap.com/saphelp_srm701/helpdata/en/38/37aa392d61407089454548b98355a8/content.htm
SRM, Strategic Sourcing Innovations
http://help.sap.com/saphelp_srm701/helpdata/en/1f/4b5f5130eb4c7db21f03fa94e5bb3f/content.htm
Tender Fee Processing
http://help.sap.com/saphelp_srm702/helpdata/EN/73/bf0af1223b405d8380cd2dfc9e5fd3/content.htm
Earnest Money Deposit Processing
http://help.sap.com/saphelp_srm702/helpdata/EN/ef/fab812e046468396262858d447d8aa/content.htm
Simultaneous Logon at RFx Response Opening
http://help.sap.com/saphelp_srm702/helpdata/EN/38/37aa392d61407089454548b98355a8/content.htm
Also as far as I am aware, by default, simultaneous logon is only available for RFXs with two-envelope RFX responses. The following is a detailed explanation of the process from 1 of my colleagues:
Two-Envelope response opening process:
01. Buyer creates a RFx/Bid invitation with the transaction type that
    is configured for two envelope bidding.
02. Enter the mandatory datas: submission deadline, bidders, items,
    permissions for technical/price/tender fee opening, etc
03. Publish RFx.
04. Login with bidder and "Participate" to receive emails.
05. If tender fee is requested, then pay tender fee with bidder user.
06. Create a Response with bidder user and submit.
07. Now you have to wait till the submission deadline has been passed
    to give the chance for the other bidders to participate in the RFx
    process.
08. After the submission deadline has been passed the buyer has to
    "Initiate Price/Technical RFx Response Opening" for a certain given
    time (which can be set earlier.)
09. A new window will pop up to start the simultaneous logon.
10. Provide password and hit the approve button.
11. The pop up window will display Technical Opener's name.
    We can see the time remaining to perform the Technical opening
12. In the next step, we will have to login to perform the technical
    opening. Do NOT close this window or do NOT logoff from the portal.
    If you think you will require more time to perform the technical
    opening you can extend this time. This will give additional minutes
    to perform the opening.
13. To perform technical opening:
    Login to WTS or open a new session of Internet Explorer and login
    to Portal. At this point in time, you will have two sessions:
    - one on your local computer
    - and one in WTS/New session
14. Open the rfx and click on Open technical rfx response.
15. The Technical Opener/Reviewer now authenticates himself/herself by
    entering the password. After it hit "Approve" button.
16. In the next step you will receive a message:
    "User approval successful"
17. The Simultaneous Logon and opening of technical/price RFx response
    is now performed.
18. Hit on Close button to close the pop up.
19. Hit on Close to close the RFx screen.
20. You have to wait till the Response opening time has been passed.
21. After the time has been passed the Response can be opened.
If the document changes in the meantime and if it needs approval (no
automatic approval is configured) then you have approve the documents
in the process with a given user.
I hope that this helps.
Kind regards,
Conor

Time remaining is increasing!

I'm trying to encode 45 minutes of HD footage using the HD DVD H.264 one hour setting.
When originally submitted, Batch Monitor quoted a time remaining of around 3 hours for the video. The batch is still processing, but the time remaining is slowly going UP instead of down. It now shows a time remaining of 9 hours 47 minutes - and it still rising!
Can anybody help?

The Apple H.264 encoder automatically calculates the optimal number of passes it needs to encode the movie as it goes along. This means that it doesn't necessarily know how many passes it will need when you first start the encoding process. That is why the time goes up.
If you want to speed up encoding, either set it to single pass (at the expense of visual quality) or optimize Compressor for your computer:
http://www.digitalrebellion.com/blog/posts/usingcompressor_with_multiplecores.html

How much time remaining on download

hey i was on itunes and i purchased two movies one is downloading fine but the other im not sure
the second movie is showing normal progress but the
time remaining bar isnt turning blue at all and it wont say how much time is left

Sorry I dont get it - Im downloading but can only see it in Apps - No idea How I see remaining download ??
Oh I see Now its under - Purchased
Jeez 4Gb odd

Share/Export Disabled - HTML publish questions

I would like to export my Keynote 09 as an HTML file, and I am currently able to do so using either Share/HTML or File/Export/HTML. But, when I do, I see no way of turning off the player (next slide, prev slide, audio, pause) that appears at the bottom of the slides. Also, none of my transistions/animations seem to work. (But the main issue at this point is how to turn off the player.) I went to the user manual and it states that to export to HTML, I should use the Share/Export menu, and shows that menu with more options than I get via the other methods. However, that option is grayed out for me. Another issue (while I'm asking) is - when I do publish to HTML, is there any way to keep the text as text, rather than have it all converted to images?
Thank you

There are a number of ways to export MP4s from a Premiere Elements project.
As Bill says, you can export it for portable devices using Share/Portable Devices/iPod.
If you're exporting it for display on the web, you should use John Cloudman's output settings in the FAQs to the right of this forum. (Although you are selecting the MOV output, it will come out as an MP4 because you are using the H.264 codec.)
http://forums.adobe.com/thread/623549?tstart=0

Share exporting...done..but showing time remaining

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