Signal Generation by duration

I am trying to output the signals created by the signal generator to an excel file.
I first try to index the array sent by the generator but it keeps giving me an error.
Is there a way to solve this problem.
Here is my source code:
The signal generator is inside the bottom case structure.
Thanks
Attachments:
Signal Output1.vi ‏593 KB

For some weird reason, your "index array" is set for a 2D array, but it only receives a 1D array. THis is typically not easy to do. Did you copied this from somewhere else?
To fix it, just disconnect the lower of the two indices.
LabVIEW Champion . Do more with less code and in less time .

Similar Messages

Digital signal generation in cDAQ- 9477 with 1ms resolution.

I am using cDAQ -9477 Digital card with 9178 chassis (USB) .I have to generate some digital signals for 2 seconds. The signal should be
0 (3ms) - 1(1ms) - 1 (2ms) & repeat the sample 0 (3ms) - 1(1ms) ……. upto 2 seconds.
I had generated samples for 2seconds with 1ms duration of each sample.
I am unable to do that with 1ms resolution in cDAQ -9477 Digital card.
Is the above signal generation is possible (each sample -1ms) ?
I am using LabVIEW2009 .I attached the code.
Kindly let me know the suggestions .
Attachments:
Digital Signal.JPG ‏7 KB
Digital.vi ‏40 KB

cDAQ chassis do not currently support hardware timed tasks for digital modules with >8 lines. The DAQmx help defines these devices as "static digital I/O modules". The "Digital I/O Consideration for C Series Devices" section in the DAQmx help describes the capabilities of digital modules on different chassis.
Unfortunately this means you are stuck with static (software timed) generation. Over USB this will affect the accuracy of your signal. You won't be able to achieve the signal you are trying to generate with the current support. Static generation will max out at roughly 1kHz, but Windows can introduce a large amount of jitter. What you really need is a hardware timed task.
This is a feature that could be added in the future. I recommend submitting a feature request, though I know that doesn't solve your problem now.

When using the LabVIEW Simulation Module, how can I start a frequency sweep with the Simulation Chirp signal generation VI at an arbitrary time after the simulation initial time?

I'm using the Simulation Loop on LV RT when interacting with some hardware (i.e. all I/O is happening in the Sim loop). I'm going to conduct a frequency sweep test on the hardware and want to use the Simulation Chirp function. However, there is no way (that I can see) to trigger the Chirp to start at some event (i.e. I click a boolean on the front panel and enter a case statement). The Chirp is tied to the global time of the Simulation loop and so are it's input parameters. Is there a way to make it relative to some time at which an event happens?

Craig,
Your solution will 'cut' the beginning of the signal and only show the signal afterwards.
To control when the chirp should start, the best option is to use the Chirp Pattern.vi ( in the Signal Generation palette) and use a Lookup table to control when to feed the time. The shipping example (in LabVIEW 2013) shows how to code using a lookup table.
C:\Program Files (x86)\National Instruments\LabVIEW 2013\examples\Control and Simulation\Simulation\Signal Generation\SimEx Chirp.vi
Then, to start from a toggled boolean, look at the example:
C:\Program Files (x86)\National Instruments\LabVIEW 2013\examples\Control and Simulation\Simulation\Signal Generation\SimEx Step.vi
and Here is the example in 2013 (in attachment):
Barp - Control and Simulation Group - LabVIEW R&D - National Instruments
Attachments:
SimEx Chirp with Delay.vi ‏241 KB

Signal Generation through pt by pt Signal

Hello,
I am acquiring signal through serial port, to analyze the signal, i am using pt bt pt signal analysis.
In order to work on it, i used sine wave pt pt signal generation. But remained un successful in generating sine wave through it.
Kindly guide me how could i generate sine wave using pt by pt.
Thanks

Hi Intelligent,
it's not a good idea to start asking by using PNs, I will ignore them in the future!
You wrote:
I already read the help and tried to solve the issue but after not receiving the satisfied results, i posted on the group. As its written in the help that the frequency is in Hz, but the value you have selected for the frequency is 0.01. So its un understandable, also the dependentence of time factor.
- What are "unsatisfying results"?
- Yes, the frequency is given in Hz and I chose 0.01Hz for sake of showing an example...
- "Dependence of time factor" is explained in the context help. Did you really read the help? Or do you have problems to understand the simple math formula provided in the help? All the parameters of SineWavePtByPt are used in that formula...
Best regards,
GerdW
CLAD, using 2009SP1 + LV2011SP1 + LV2014SP1 on WinXP+Win7+cRIO
Kudos are welcome

How to run fx ,signal generation example project in eclipse

Hi,
i run the helloworld sample project ,it works fine in ecllipse,cmd prompt window and i am try to run FX and signal generation sample program in eclipse ,i can't able to run in eclipse but i can able run in cmd prompt window.i want to know whether ocep projects can be run only through cmd prompt or both (cmd prompt and eclipse). if u have solutions to run in eclipse means help me please.Thanks in advance

Hi,
I got this below error in startDataFeed.cmd in singal generation ,but server started.
C:\Oracle\Middleware\ocep_11.1\samples\domains\signalgeneration_domain\defaultse
rver>startDataFeed.cmd
'startDataFeed.cmd' is not recognized as an internal or external command,
I got this below error in FX sample program ,but server is started and program is working fine.can just help what is the error in sample program i want to know.
<Aug 7, 2012 11:46:03 AM IST> <Warning> <Spring> <BEA-2047006> <Work {0} terminated with exception = commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketEuro configured with illegal port [9,013]
commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketEuro configured with illegal port [9,013]
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkStatus.setThrowable(CommonjWorkManagerImpl.java:268)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:206)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
Caused By: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketEuro configured with illegal port [9,013]
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.setupServerConnection(SocketAdapterImpl.java:139)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.run(SocketAdapterImpl.java:114)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl$$FastClassByCGLIB$$6267eec3.invoke(<generated>)
     at net.sf.cglib.proxy.MethodProxy.invoke(MethodProxy.java:149)
     at org.springframework.aop.framework.Cglib2AopProxy$CglibMethodInvocation.invokeJoinpoint(Cglib2AopProxy.java:700)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:149)
     at com.bea.wlevs.ede.impl.EventManagerAccessorProxy.invoke(EventManagerAccessorProxy.java:30)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at com.bea.wlevs.ede.impl.EventBeanProxy.invoke(EventBeanProxy.java:38)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at org.springframework.aop.framework.Cglib2AopProxy$DynamicAdvisedInterceptor.intercept(Cglib2AopProxy.java:635)
     at com.bea.wlevs.adapter.defaultprovider.internal.LoadGenAdapterImpl$$EnhancerByCGLIB$$5d089e06.run(<generated>)
     at com.bea.wlevs.spring.RunnableBeanPostProcessor$RunnableWrapper.run(RunnableBeanPostProcessor.java:118)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:204)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
>
<Aug 7, 2012 11:46:03 AM IST> <Warning> <Spring> <BEA-2047006> <Work {0} terminated with exception = commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketAmer configured with illegal port [9,011]
commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketAmer configured with illegal port [9,011]
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkStatus.setThrowable(CommonjWorkManagerImpl.java:268)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:206)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
Caused By: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketAmer configured with illegal port [9,011]
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.setupServerConnection(SocketAdapterImpl.java:139)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.run(SocketAdapterImpl.java:114)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl$$FastClassByCGLIB$$6267eec3.invoke(<generated>)
     at net.sf.cglib.proxy.MethodProxy.invoke(MethodProxy.java:149)
     at org.springframework.aop.framework.Cglib2AopProxy$CglibMethodInvocation.invokeJoinpoint(Cglib2AopProxy.java:700)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:149)
     at com.bea.wlevs.ede.impl.EventManagerAccessorProxy.invoke(EventManagerAccessorProxy.java:30)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at com.bea.wlevs.ede.impl.EventBeanProxy.invoke(EventBeanProxy.java:38)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at org.springframework.aop.framework.Cglib2AopProxy$DynamicAdvisedInterceptor.intercept(Cglib2AopProxy.java:635)
     at com.bea.wlevs.adapter.defaultprovider.internal.LoadGenAdapterImpl$$EnhancerByCGLIB$$5d089e06.run(<generated>)
     at com.bea.wlevs.spring.RunnableBeanPostProcessor$RunnableWrapper.run(RunnableBeanPostProcessor.java:118)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:204)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
>
<Aug 7, 2012 11:46:03 AM IST> <Warning> <Spring> <BEA-2047006> <Work {0} terminated with exception = commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]csvTestData configured with illegal port [9,014]
commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]csvTestData configured with illegal port [9,014]
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkStatus.setThrowable(CommonjWorkManagerImpl.java:268)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:206)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
Caused By: java.lang.IllegalArgumentException: [Adapter:2041001]csvTestData configured with illegal port [9,014]
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.setupServerConnection(SocketAdapterImpl.java:139)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.run(SocketAdapterImpl.java:114)
     at com.bea.wlevs.adapter.defaultprovider.internal.CSVGenAdapterImpl.run(CSVGenAdapterImpl.java:43)
     at com.bea.wlevs.adapter.defaultprovider.internal.CSVGenAdapterImpl$$FastClassByCGLIB$$1d34d8cd.invoke(<generated>)
     at net.sf.cglib.proxy.MethodProxy.invoke(MethodProxy.java:149)
     at org.springframework.aop.framework.Cglib2AopProxy$CglibMethodInvocation.invokeJoinpoint(Cglib2AopProxy.java:700)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:149)
     at com.bea.wlevs.ede.impl.EventManagerAccessorProxy.invoke(EventManagerAccessorProxy.java:30)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at com.bea.wlevs.ede.impl.EventBeanProxy.invoke(EventBeanProxy.java:38)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at org.springframework.aop.framework.Cglib2AopProxy$DynamicAdvisedInterceptor.intercept(Cglib2AopProxy.java:635)
     at com.bea.wlevs.adapter.defaultprovider.internal.CSVGenAdapterImpl$$EnhancerByCGLIB$$3ec938ea.run(<generated>)
     at com.bea.wlevs.spring.RunnableBeanPostProcessor$RunnableWrapper.run(RunnableBeanPostProcessor.java:118)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:204)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
>
<Aug 7, 2012 11:46:03 AM IST> <Warning> <Spring> <BEA-2047006> <Work {0} terminated with exception = commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketAsia configured with illegal port [9,012]
commonj.work.WorkException: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketAsia configured with illegal port [9,012]
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkStatus.setThrowable(CommonjWorkManagerImpl.java:268)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:206)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
Caused By: java.lang.IllegalArgumentException: [Adapter:2041001]fxMarketAsia configured with illegal port [9,012]
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.setupServerConnection(SocketAdapterImpl.java:139)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl.run(SocketAdapterImpl.java:114)
     at com.bea.wlevs.adapter.defaultprovider.SocketAdapterImpl$$FastClassByCGLIB$$6267eec3.invoke(<generated>)
     at net.sf.cglib.proxy.MethodProxy.invoke(MethodProxy.java:149)
     at org.springframework.aop.framework.Cglib2AopProxy$CglibMethodInvocation.invokeJoinpoint(Cglib2AopProxy.java:700)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:149)
     at com.bea.wlevs.ede.impl.EventManagerAccessorProxy.invoke(EventManagerAccessorProxy.java:30)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at com.bea.wlevs.ede.impl.EventBeanProxy.invoke(EventBeanProxy.java:38)
     at org.springframework.aop.framework.ReflectiveMethodInvocation.proceed(ReflectiveMethodInvocation.java:171)
     at org.springframework.aop.framework.Cglib2AopProxy$DynamicAdvisedInterceptor.intercept(Cglib2AopProxy.java:635)
     at com.bea.wlevs.adapter.defaultprovider.internal.LoadGenAdapterImpl$$EnhancerByCGLIB$$5d089e06.run(<generated>)
     at com.bea.wlevs.spring.RunnableBeanPostProcessor$RunnableWrapper.run(RunnableBeanPostProcessor.java:118)
     at weblogic.work.commonj.CommonjWorkManagerImpl$WorkWithListener.run(CommonjWorkManagerImpl.java:204)
     at weblogic.work.SelfTuningWorkManagerImpl$WorkAdapterImpl.run(SelfTuningWorkManagerImpl.java:545)
     at weblogic.work.ExecuteThread.execute(ExecuteThread.java:256)
     at weblogic.work.ExecuteThread.run(ExecuteThread.java:221)
>
<Aug 7, 2012 11:46:03 AM IST> <Notice> <Server> <BEA-2046000> <Server STARTED>

Como puedo instalar ISDB-T/Tb Digital Video Signal Generation Toolkit - MaxEye Technologies en labview 2014

Hola me gustaria que me ayuden con un problema que tengo, descargue ISDB-T/Tb Digital Video Signal Generation Toolkit - MaxEye Technologies evaluation pero cuando lo quiero instalar me aparece un mensaje diciendo que primero debo instalar labview 2012 pero yo tengo labview 2014, como puedo instalar esta herramienta sin tener que cambiar la version de mi labview?

Saludos Mafilu,
Gracias por utilizar los Foros de Discusión de National Instruments, con respecto a tu consulta creo que lo mejor será que contactes directamente al equipo de soporte de MaxEye Technologies para corroborar si existe alguna necesidad especial, o bien, si tienen alguna alternativa.
Support Information
For technical support, contact MaxEye Technologies at:
Phone: +91-80-2527-0024, +91-94-4806-7717
Email: [email protected], [email protected]
Web: maxeyetech.com
Quedo al pendiente, saludos.
David P.
National Instruments
Applications Engineer
www.ni.com/soporte

Segment signal generation

Hi!
How is it possible to generate such a signal (picture attached)?
https://pp.vk.me/c622024/v622024951/33e6f/I3zJNTMGiU0.jpg
A link to the answer (if there is one in this forum) would be awesome.
Thanks
Solved!
Go to Solution.
Attachments:
I3zJNTMGiU0.jpg ‏50 KB

Many thanks. I did it using Ramp pattern VI and for loop.
The result is attached.
Now I need to sent this result to control and simulation loop.
This signal have to be desired position of my actuator insted of Knob (now I set the desired position using knob). check the attached vi.
But as I found out it is impossible to put 'for loop' inside of 'control and simulation loop'.
'control and simulation loop' also do not want to read updated signal from the outside, if I place my signal generation (using Ramp pattern VI and for loop) outside of 'control and simulation loop'.
Coul you please suggest somth?
THANKS
Attachments:
Ramp pattern.vi ‏16 KB
VCA by Knob.vi ‏672 KB

How to trigger temperature acquisition (6024E) at the start of signal generation from NI5411?

I'd like to begin/end acquiring temperature data with the 6024E after the start/stop of the signal output from the 5411. What is the best way to accomplish this? is software or hardware triggering better?

Rudy,
Using a hardware trigger is definitely the more precise method. I would suggest that you consider using markers from the NI 5411 to trigger the NI 6024E. Information concerning this topic is available in the NI Signal Generators Help. Specifically, it is available in the following location:
Contents >> NI Signal Generators Help >> Devices >> NI 5411 >> Waveform Generation >> Marker Events
If you do not have the NI Signal Generators Help, it can be downloaded from the following location:
NI Signal Generators Help (NI 5401/5404/5411/5421/5431)
Once you have exported the appropriate makers, numerous examp
le programs exist that demonstrate how to trigger the NI 6024E. If you are using LabVIEW, I would suggest that you examine the Acquire N Scans Digital Trig.vi example.
Good luck with your application.
Spencer S.

Preventing a glitch during signal generation

I’ve got two high speed digital IO cards (NI PCI-6541) generating simultaneous waveforms, and I’m getting a 120 – 150 ns glitch from one during the generation process. The waveforms have ~ 200k samples at a sampling rate of about ~ 20 MHz.
For each board, I call this sequence of functions:
niHSDIO Init Generation Session.vi
niHSDIO Assign Dynamic Channels.vi
niHSDIO Configure Sample Clock.vi
niHSDIO Export Signal.vi
niHSDIO Configure Generation Mode.vi
niHSDIO Export Signal.vi
niHSDIO Configure Generation Repeat.vi
niHSDIO Write Named Waveform (1D U32).vi
niHSDIO Write Script.vi
niHSDIO Get Session Reference.vi
It’s the “niHSDIO Write Named Waveform (1D U32).vi” function that causes the glitch. I’ve run into a similar thing before and it was the signals briefly going to a high impedance state during an initialization call; is there some way to prevent that?

Hello All,
This issue was resolved by changing the initial state in the niHSDIO Init Generation Session.vi. The "glitch" occurred because the niHSDIO Init Generation Session.vi was configured to reset the device at the begining of the program. This set the device into a high impedance state. By changing the input so that the device did not reset we were able to eliminate the problem.
Matt Anderson
Hardware Services Marketing Manager
National Instruments

NI-6062E FM signal generation with DAQmx

Hi everyone,
I am trying to use the NI-6062E DAQ card to generate an AC voltage signal and I found 2 relevent example:
(1)Cont Gen Voltage Wfm-Int Clk.vi found in LV7.1 DAQmx examples
(2)Function Generator with FM.vi also found in LV7.1 examples
But I have it hard to implement the 2nd vi directly into the 1st one and it looks like I have to make change to the subVIs?
I am trying to modulate a 500Hz sine wave with frequency of 10Hz, can anyone help?
Thank you!

rpursley8 wrote:
Are you trying to do this as a real-time signal or are you generation the waveform ahead of time and sending it out?
An FM modulated signal is defined as
f(t) = A*cos(2*pi*fc*t + m*sin(2*pi*fm*t))
where
A = amplitude of signal
fc = carrier frequency (500 Hz)
m = modulation index (how big of a swing in frequency that you want)
fm = modulation frequency (10 Hz)
pi = pi
so a formula node might be the easiest way. To generate a complete cycle, you will have to generate 0.1 seconds of data, then you could repeat it continuously without any discontinuitues.
Clearly the carrier and modulation can be something other than sinusoids, but this is how it is usually represented.
Attached is an example of generating the waveform.
Hi Randall,
Thank you for your reply, yes and I am trying to generate this real time signal on the NI-6062E Analog Output channel, but I find it difficult to insert either your example or the example FM vi from LV7.1 into the following VI?
I think it also needs to deal with hardware channel config (for sample clock rate) using DAQmx? or I need to make change to the subVI such as Waveform Buffer Generation.vi or even further the Basic Function Generator.vi?
Thank you for your patient.
Regards
Rolly
Attachments:
Cont Gen Voltage Wfm-Int Clk.vi ‏83 KB

DAQmx with signal generation

Hello,
I am working on converting my current test code that used Traditional DAQ to DAQmx. I need some help with DAQ Waveform Generation.
In my current code I am using the Traditional DAQ to send a Sinewave output on on the DAC0Out on my PCI-6036E card. I have it set-up so I can runt he VI and when the Vi stops the Signal Keeps going until I tell it to stop. I need to do the same thing with DAQmx. I found that the example 'Cont Gen Voltage WFM-INT Clk-Variable Rate.vi does everything I need but when the VI stops so does my signal. What can I do to make it so the signal stays running when my vi stops.
this VI is a Sub in my program, the user is able to control a boolean to start and stop the waveform, I cannot keep it in a loop as they may want to turn ont he waveform and perform other tasks then turn it off.
I am trying different things as well, but any help would be appreciated.
Oh yeah, this is an XP machine running LabVIEW 8
Jeff D.
OS: Win 7 Ultimate
LabVIEW Version: 2011,2010,2009 installed
Certified LabVIEW Architect

Hello Jeff,
To continue to output a signal after you have stopped and closed the VI, you use the auto cleanup terminal on the DAQmx Create Channel VI. Auto cleanup specifies if LabVIEW automatically destroys the
task when the application completes execution. If auto cleanup is FALSE, LabVIEW does not automatically destroy the task until you exit
LabVIEW. But you can use the DAQmx Clear Task VI to manually
destroy the task.
I'm attaching a modified version of the Cont Gen Voltage WFM-INT Clk-Variable Rate.vi that continuous to generate the AO signal until you close LV.
Good luck!
Micaela N
National Instruments
Attachments:
Modified Cont Gen Voltage Wfm-Int Clk-Variable Rate.vi ‏47 KB

I have a problem with a vi that crash and stops the signal generation.

I want to control several pumps and valve at the same time. Three of them are comanded by a board installed in other computer, so that I have to comunicate with them by a TCP/IP comunication. The others one are controled by signals sent by a PCI-6024 E board which is installed in my computer. The problem is that I want to create a vi that controls every equipment at the same time. I did a Vi that is in attach, but the problem is that when I run the vi it works during a certain time, but after 10 minutes (more or less) it stops to send the signals to the pumps. Could someone help me?
Attachments:
controlo_bombas_caudais.vi ‏98 KB
valvula.vi ‏53 KB

You did not include your subVIs so not much can be inferred. Several points of poor programming jump out
1. Use time delays in your loops to keep them from racing
2. Put the Open Application Ref and Open VI Ref before the start of the loop and the Close Ref after the loop

DIGITAL SIGNAL GENERATION

Hi!
I want to generate a digital signal (0-5V) in order to turn on and off an hydraulic pump. The time on (high) and time off (low) are specified by a MatLab code, so that once the pulse has finished one cycle, the program should be go again to MatLab code and take two times again. Then it should generate the signal again.
Thank you for the help.
Miguel

Thanks for the reply.
I have a system with an hydraulic pump, power supply, transistor and computer. I would like to send a digital pulse from my computer (0-5V) to the transistor. The transistor then closes a circuit (power supply and pump), and the pump starts running.
Then, I would like that each sample (each pulse) has specific width (time on), and also specific time off before it starts with other sample. These times (time on and time off) are computed by a MatLab code.
I'm working with DAQmx drivers and I also have a BNC 2110.
I also attach my code in Labview that I am trying to modify.
Thanks a lot.
Regards,
Miguel
Attachments:
Gen Dig Pulse Train-Finite_original.vi ‏22 KB

Arbitrary signal generation acquire 5411 5911

An arbitrary signal generated on a PCI-based NIFGEN(5411) is not acquired correctly on a PCI-based NISCOPE (5911). I use RTSI to synchronize the two boards (5911 is the master). When the 5411 board has generated the waveform the 5911 board should start acquiring immediately, but it seems like the board does not receive the correct data the first several times (It jitters around zero). Does anyone know what the problem might be (I have attached my VI)? If not does anyone know how to examine the data actually generated by the 5411 board?
Attachments:
5911-5411_interface.zip ‏144 KB

You may want to post your query under the Measurement Hardware section of the forum for a faster response.
Rgds,
Khalid

High Speed Clock Signal Generation Using FPGA Ouput

Hi,
This a screen shot of a LabVIEW FPGA program. Here I am trying to generate 5MHz Clock signal at Connector 0 DIO12. But I get around 2MHz when I measure the signal using an oscilloscope. Would some tell me what’s wrong ?
LabVIEW 2011
FPGA Target : PXI 7841
I set DIO 12 to Nerver Arbitrate in the property setting.
Solved!
Go to Solution.

I'm not certain but maybe some of the delay is happening because you are changing the mode of the pin. According to the specs on the card it is capable of having a Maximum Clock Rate of 40MHz under the DIO section. So if you are purely doing digital reads, or digital writes you should be able to update/read 40,000,000 times a second. If you perform a read, which can take up to 1/40M of a second, then invert which takes some time but practically none, then another write which can take up to 1/40M of a second, your loop rate should still be faster than the 10MHz you showed. That's why I suspect there is time involved in changing over the pin from a read mode to a write.
If you try to do something similar with the analog you'll notice the maximum update rate is only 1MHz. So while your logic and code can run at 40MHz you can only update the analog value at 1MHz. Because of this in the past I have had two loops. One running a at the maximum clock rate doing the logic calculations, and then sending the result to another loop that updates the output at the maximum rate which in the case of an analog out is only 1MHz.
Unofficial Forum Rules and Guidelines - Hooovahh - LabVIEW Overlord
If 10 out of 10 experts in any field say something is bad, you should probably take their opinion seriously.

Signal Generation by duration

Similar Messages

Maybe you are looking for