Sim. arb. signal within Timed Loop?

Hi there,
Is there any inherent reason I couldn't/shouldn't put a Sim Arb Signal VI within a timed loop? I have a scenario in which i need to modulate an arbitrary signal as the experiment is being run. I've placed the express vi inside a timed loop set to execute every millisecond. The express VI is setup to generate a single point of a arb signal with a dt=1. It seems however that it generates the whole signal each time the loop is called. Is there an appropriate example or tutorial somewhere out there in cyberspace?
Apologize for not posting an example, but I am working from home tonight.
Regards,
Matthew Pausley
NC State University
Raleigh,NC

Matthew,
I have tried making the simulate arbitrary signal vi output a singal point using your suggestions and it worked. Perhaps you need to compare the VI you are using with this one.
I hope this helps.
Steven T.
Message Edited by Steven T on 10-16-2006 11:46 AM
Attachments:
example2.vi ‏110 KB

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Using timer/counter with PCI-6221/USB-6210 to control timed-loop VI

Dear all,
I need to ask about two devices and one of their functionalities, PCI-6221 and USB-6210. For our NI-based system, we need to control some timings in a Timed-Loop vi, for that currently we are using PCI-6221 and we give external TTL signal (at 1 kHz) to it,
recenntly we need to make some changes and for that we found USB 6210 DAQ to be more suitable, but we need to clear ourselves on some specific things.
Can the counter/timers functions available in the either PCI 6221 or USB 6210 can be used to control the Timed-loop VI by giving external clock or by using their own internal clock source?
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Solved!
Go to Solution.

Ben,
I having read previous email which I send earlier with general overview, we discussed in more detail within our team and I am giviing the specific answers.
Please check in RED the most recent answers. Blue are the questions/suggestions by your side.
1.    Using Internal hardware clock of PCI-6221 would enable us get rid of external clock, but how to divert the internal hardware clock to the current settings. Any idea (can you provide us with some reference manul for otherwise). I mean is there some flag-bit etc. or VI
2.       Is it also meant that with the installation of RTOS the timed-loop can directly get the timing source from the internal hardware clock PCI-6221? --- How???
3.       In order to make desktop to work as RT system, what is the hardware (motherboard, processor, etc..) requirement? What are the LabVIEW modules (specific name) that needed to be installed? Our platform is LabVIEW 8.6. (Currently we have windows-7 with i7 core processor)
What kind of application are you intending for this system? ---- high-speed laser scanning system.
Are you most concerned about accuracy, speed, or responsiveness? To control the laser mirror scanner to move at 1 kHz or 2 kHz speed. On the other hands, using PCI-5105 (128 MB memory) as a DAQ for real-time/on-the-fly data processing.
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NI Support Resources
NI Training Resources

Unable to run Timed Loops

Bit of an odd one that had me scratching my head.
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A restart of the system, and rerunning the same VIs, and no problems since.
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The timed loop is used to read all elements from a DMA FIFO and load them into a buffer FGV, which spits out packets of N samples long once they've assembled within the FGV. Ordinarily, I'd do this with a timed while loop and be perfectly happy to do so. However, the elements are actually an interleaved array, meaning that I have to demux them in the correct order that they were loaded.
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Producer consummer loop and timing loop

Hi,
I have to acquire 32 signals and record each signals. I would like to acquire my signals at a sample rate of 100kHz. But I tried with a different sample read and I have always an error of overwritten.
In my producer loop I read and display all signals and in my consumer loop I record and resample my signal.
But I thought It was maybe I haven t a timing loop in my producer and consumer loop and it slow my read in the buffer.
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Thank you very much for your response
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Why did you start a new message thread?
You were already being helped here.

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When I use a timed loop I get an "Unrecoverable Error" (status light on FP-20xx blinks four times) after compile and run - although not immediately. When I replace the timed loops with regular while loops everything is o.k.
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I was trying to use the Time Loop in a FPGA target. I lost all day trying to figure out why the Time-Loop worked at a fixed period instead of the period I programmed. Finally I found out in this website that the time-loop works different in a FPGA target than in a normal VI. National Instruments should add a hint on the "Context Help" about this.
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Dear
Issac,
When you code VI for the
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As mentioned in the context help and the help of LabVIEW, If you use the Timed Loop in an FPGA VI, the loop
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Chapter 7 of LabVIEW 8 FPGA Module Training
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Who know the difference between the two Timed Loop structures in NI's examples named PAC Simulation.vi?

My LabVIEW version is LabVIEW 8.0.
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After I posted this, I realized there was one more "Time" clock, namely the Time node on the Event structure. How is this clock (which I will call ET, for Event Time) related to the Global Start Time (or GST) and the TimeStamp (TS)?
ET represents time in milliseconds, using a U32. The largest value that can be represented is roughly 4 billion, but there are more than 30 billion milliseconds per year. Hence this "clock" cannot directly keep the same time as the GST or TS.
However, on the PC, if you multiply the ET value by a million (thereby converting the time to nanoseconds) and compare this value to GST, you'll see they are basically the same. Thus, on the PC, ET and GST are "in sync", but not in sync with TS.
On a real-time PXI system, we already established that TS and GST are "in sync" -- what about ET? Curiously, this does not seem to be synchronized with anything.
A Word to the Wise -- when I originally added the Event structure, I synchronized it with the Timed Loop using a Value(Signalling) property node, which worked fine on the PC, but failed to fire on the PXI. I'd forgotten that you can't use this trick on real-time systems, as they have no Front Panel objects, hence the implementation using Dynamic Events.
Attachments:
TS GST ET VI.png ‏16 KB

Timing Loop won't Execute

I think this is a labVIEW bug, but I'm looking for a work around or a 'gotcha'.
I was attempting to create a timing loop for the purposes of sychronizing two sections of code within a VI. The timing loops would not execute and so as part of the debugging process I created a simple empty timing loop with a 'stop button' in it. Put a probe on the wire between the stop button and the stop terminal of the timing loop and executed my VI. The Timing loop never executed.
I then created a new VI to continue debugging the timing loop: I created a new VI and a new timing loop with only a stop button, placed the probe in the same place, (between the button and the stop terminal) and ran the 'untitled vi'. In the new vi the timing loop ran as intended.
All I can think is that there is some VI property in my rather complicated VI that prohibits timing loops but is not producing an error or warning. I did check the VI properties and though they are not default there isn't anything that should be interfering with running a timing loop (e.g. critical execution).
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-Regards
eximo
UofL Bioengineering M.S.
Neuronetrix
"I had rather be right than be president" -Henry Clay
Attachments:
timing loop.PNG ‏9 KB

The attached image of the first post is the disfunctional version, Attached to this is a segment of the VI with the example disfuctional timing loop at the bottom right.
-Regards
eximo
UofL Bioengineering M.S.
Neuronetrix
"I had rather be right than be president" -Henry Clay
Attachments:
Timing loop not working.PNG ‏68 KB

Priority limits on a timed loop

Hi,
With reference to the value of priority in a timed loop, the help says that this value must be between 1 and 65,535.
Anyone know what these limits are referred?
Thanks for your time...
Solved!
Go to Solution.

amflores wrote:
Hi,
With reference to the value of priority in a timed loop, the help says that this value must be between 1 and 65,535.
Anyone know what these limits are referred?
Thanks for your time...
Timed loops run in a dedicated execution system at a priority above high priority but below "Time Critical" if there is more than one timed loop running the timed loops priority value is used to signal the OS which loop should get the larger amount of processor time. The lower the number the higher the priority requested. Some OS's even respect that number. Some do their own scheduling anyway.
Jeff

Timed loop works not well

Hi,
how can I get a digital signal shorter than 25 microseconds? I am using
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Tim,
Sorry I don't know much about RT but you may find a better response to your questions if you post in the real time forum.
http://forums.ni.com/ni/board?board.id=280
Brian

Timed loop and CPU usage

Platform is WIN_XP Pro and machine is a P4 at 2.5Ghz with 512 Mb ram.
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Hello,
It sounds like an interesting problem. It would be worth some experimentation to figure out what's going wrong - attempting to decouple major "pieces" of the code would be helpful. For example, you could try breaking your code into multiple loops if that makes sense in your architecture, but perhaps you could even eliminate all but one of the loops to begin with, and see if you can correlate the problem to the code in just one of your loops.
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Best Regards,
JLS
Best,
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Just drop them on the Loop Browser and the rest should be taken care of.

Questions about parallel and series sturcture in SCTL (single clock timed loop) in FPGA VI

I am using LV 8.2.
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Thank you!

Sorry, I am afraid that you have misunderstood my meaning.
Here is the method you suggested before:
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I have a timed loop triggered by the sample clock of a DAQ-Card. The sample Clock is 8 kHz and the loop will run with dt = 4. Normally the loop is running without finished late[i-1]. But from time to time it happens that the loop is running extremly longer which means instead of 0.5 millisec it needs 4 - 5 millisec. It seems this doesn't never occur while accessing DAQmx.
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Don't forget to give Kudos to good answers and/or questions

To keep you informed:
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Waldemar
Using 7.1.1, 8.5.1, 8.6.1, 2009 on XP and RT
Don't forget to give Kudos to good answers and/or questions

Sim. arb. signal within Timed Loop?

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