Problem programming Timed Loop period

Question

I was trying to use the Time Loop in a FPGA target. I lost all day trying to figure out why the Time-Loop worked at a fixed period instead of the period I programmed. Finally I found out in this website that the time-loop works different in a FPGA target than in a normal VI. National Instruments should add a hint on the "Context Help" about this.
Isaac

Answer 1

Dear
Issac,
When you code VI for the
FPGA target you should always thing that you are very close of the hardware.
As mentioned in the context help and the help of LabVIEW, If you use the Timed Loop in an FPGA VI, the loop
executes one subdiagram at the same period as an FPGA clock.
The SCTL provides faster
execution of the LV FPGA diagram, allowing each cycle of the loop to execute in
one clock cycle. This enables up to update a signal line at the FPGA base clock
frequency. The SCTL also optimizes the code generation so that the code on
the FPGA is more efficient and uses less FPGA real estate. However, there are
several restrictions on the code implemented inside of a SCTL
To have more details
about the timed loop (SCTL) you can have a look at the following link :
Chapter 7 of LabVIEW 8 FPGA Module Training
help:Timed Loop (FPGA Module)
Using Single-Cycle Timed Loops to Optimize FPGA VIs (FPGA Module)
Best regards,
Nick_CH