Simuntaneous arming of counters

Hey guys,
I am trying to configure seven counters on a PCI6602 to simulate a quadrature encoder signal(Channels A,A',B,B',Z,Z') and a regular encoder signal(Channel X). The quad encoder signal works fine and was done by setting up Pulse Train Generation on channel A, and Retriggerable pulse generation on the other 5 channels. I then use channel A as the gating signal for the other 5 channels. This works beautifully! Now I am stuck though. To generate a regular encoder signal, I need to output a pulse train that starts on the same rising edge as channel A (with no delay!), but has twice the frequency of channel A. I have tried triggered pluse train generation (too much delay in Channel X), and retriggerable pulse generation(can't g
et a frequency that is twice that of channel A)with no success. Has anyone got any suggestions? I am using the latest version of NIDAQ (6.9.3) with MS Visual Basic (no CW components) on a PCI 6602 counter board.
Thanks,
Dave

Dave,
Given that you know the frequency of A, so you can specify it's double for X, we can try and do the following ...
Set up the pulse generation on X to be reverse (negative) polarity. Then setup X to be armed by a rising edge hardware trigger (triggered pulse generation). Use A to trigger X. Since you are using reverse polarity for X, and the width will come before the delay of the pulse, then the X train will start when the A train starts. The only delay you will have is a slight, and unpreventable, hardware delay, in the nanosecond range.
Without using reverse polarity, the delay would come before the width, and you would notice a large delay, which depending on your frequency and duty cycle, could be too large.
Regards,
Justin Britten
Applications Engineer
National Instruments

Similar Messages

Simultaneously latching multiple counters (AKA "strobe")?

How do you simultaneously latch values in multiple counters, at arbitrary times, for later reading?
A physical system generates several kinds of events to be counted by different counters, none of which events are strictly periodic or mutually synchronized (most of them are radioactive decay events, on the order 10^-3 to 10^5 per second average). It is critically important to count them all. At somewhat irregular intervals a few dozen milliseconds apart, I have the opportunity to read the counts, and it is also critical that whenever I read them, the counts are all captured at the same time, though it is not important exactly when this time is or how close in time I read them. Note: it is defining the end of one count period and start of the next that is time critical - not returning the count value to the calling program, which can happen whenever convenient.
I've used other counters that have a strobe-and-latch feature in past versions of this system, including Advanced Micro Devices' Am9513 and the good old 8254. When a read opportunity happens, I programatically strobe the counters then read each one's latched values at leasure, while the counters themselves continue counting. But I haven't found strobe-and-latch in either of my two NI hardware systems or in any of the LabVIEW vi's, properties, or examples. Is it there someplace, maybe by a different name?
I haven't found an example vi that simultaneously buffers counts in different counters. But it looks like some combination of the "Count Digital Events-Buffered-Continuous-Ext Clk.vi" example vi and the "Duplicate Count Prevention" method described in my DAQPad-6259 docs might get me what I want, but I'm not sure. I've attached one of my attempts to make this work, "SimultaneousCountBuffering01.vi". I have a single benchtop signal generator sending a 1 kHz signal to my DAQPad, where it's wired to both counter source terminals. This vi reads both counters at slightly different times on an irregular schedule repeating at about a half second. But it also first drives a digital output line high and low. This output is physically wired to both counter gate terminals. The DAQPad docs say that when counting in this mode, the counter is always counting regardless of the state of the gate, but at every positive edge on the gate, the count is buffered for subsequent reading. It's not important whether the readings are cumulative or get rezeroed because it's easy to use a shift register to change this anyway.
But I haven't gotten this vi or others like it to do anything useful. In this particular version, the counter reads time out. Maybe this means there's nothing sitting in the counter buffer? The examples don't seem to show anything making the counter buffer counts, so I guess that's done by the property node selecting Duplicate Count Prevention counting mode. I've checked various combinations of the digital out line state in this vi, by the way, but still the timeout happens. In my other attempts the counts are always zero, or occasionally jump by thousands, or only one counter will occasionally see only one count. Simpler vi's (that don't attempt the Duplicate Count Prevention and don't get synchronized count values) do work, and the counters both count at the expected rate.
Am I on the right track, using Duplicate Count Prevention?
If not, what approach should I be taking?
Even if this is the wrong approach, I still wish the vi did something, and am curious what I'm leaving out. Anybody know?
Thanks!
Attachments:
SimultaneousCountBuffering01.vi ‏64 KB

I don't have LV handy here, but I took a quick look at your OneLoop and TwoLoop attachments. If I remember correctly (I may be mixing those up with a couple other things I looked at), you face the following significant issues:
A. Need dataflow sequencing to help enforce execution sequence. With multiple data acq tasks, it's very typical to use the wind the error cluster from one task to another as a means to enforce execution sequence.
B. Need an overall scheme that doesn't keep configuring, running, and clearing each task in a software loop.
Let me roughly describe an approach I'd suggest:
1. Create a "dummy" AO task solely for the purpose of using its sample clock as a strobe for buffering your edge counts. Configure it for Continuous Samples using DAQmx Timing.vi The sample rate you choose will determine how often count values are captured ("strobed"). You may also need to set the property to "Allow Regeneration", found under one of the DAQmx Property Nodes (probably either the Channel or Write node). Write an array full of 0 values to the output buffer using DAQmx Write. (The actual value doesn't matter to the program, but 0 volts should be a safe value if you've got anything wired to your analog output terminals.)
2. Create 2 similar edge counting tasks with your counters. Both should be configured to use a digital "Arm Start" trigger using a DAQmx Trigger property node. That will guarantee that they are sync'ed at time=0. When you call DAQmx Timing.vi, wire in the input that lets you specify sampling using the AOSampleClock.
3. My personal choice for getting them all started in the right order would go like this. The counters would use the falling edge of the AOSampleClock as an "Arm Start" trigger and the rising edge of the AOSampleClock as their sample clock. The counter tasks are started before starting the AO task. After starting the AO task, the falling edge of the 1st AOSampleClock will "arm" the counters to start counting their edges simultaneously. The rising edge of the 2nd AOSampleClock will "strobe" the count values into the counter tasks' data acq buffers. Each subsequent rising edge will buffer the next counts.
4. Duplicate Count Prevention may need to be specified if there's a chance you might not see any edges to count between 2 consecutive sample clock strobes.
5. When you read from the counter tasks, be sure to read the same # of samples from each task. Then you can subtract the arrays to get your count differences, knowing that the counts correspond to the exact same interval of time.
-Kevin P.

Simultaneously read 4 counters on 6602 card

I have Labview 5.1 and a NI 6602 counter/timer card. I need to start, make several readings, and stop 4 counters simultaneously (ttl pulse input). It is critical that they all be started and the final reading taken at the same time. I have tried several of the simple VIs and example codes but I am new to counter programming and don't know enough to make them work. If someone could provide information/explanation or example code, it would be most helpful.
Thanks
Ron

Ron
To simultaneously arm multiple counters, you must enable start trigger for each counter. When a start trigger is enabled on a counter, it awaits this trigger after it has been armed by software. The counter begins whatever function it has been programmed for after receiving this start trigger.
In LabVIEW, use the 'Counter Start Trigger (NI-TIO).vi' to enable the start trigger.
Brian

Using AI Sample Clock to Trigger Counter Samples

My basic question is: Is the ai\SampleClock signal only active while an analog input task is running?
The details are:
I have an X-series PCIe-6321 multifunction DAQ card. It is controlling a SCXI chassis and has a SCXI-1180 and SCXI-1302 so I can control analog inputs of the chassis as well as access the 4 counter on the card. My application requires that I use all 4 counters to measure a frequency input signal and synchronize the samples to the analog input signals. I have created 5 tasks, 1 for the AI and 1 for each counter.
I am using LabVIEW 8.6.1 with the latest NI-DAQ drivers on and 64-bit Vista OS
1. Are there any driver or hardware restrictions that would cause this solution not to work?
2. Can I use the ai\SampleClock as in input sample clock for each of the frequency tasks? If I do this will the sampling start be syncronized? I.e. if I start each of the frequency tasks first, will they wait until the AI task is started before they start sampling?
3. If that doesn't work, do I need to route the sample clock from the AI task to a PFI line (PFI1) and then use that as input to the frequency task sample clock?
I usually do option 3 when synchronizing two cards in PXI chassis and only use the software task start in stead of of synchronizing on a digital start, since the sample clock will control the samples anyway. I need to know if the same behaviour works with the scenario above.
Thanks,
Bob
Prolucid Technolgies Inc.
Solved!
Go to Solution.

Hi Bob,
I can confirm that the ai/SampleClock will only be active while the AI task is running. As far as the other questions go:
1. You'd have to provide more information about what you looking to do exactly, but there is no problem with routing the sample clock of the Analog Input task to be used with the Counters. I would read through the section of the X Series User Manual that discusses sample-clocked frequency measurements (starting on page 7-16) for some more information about what is actually going on during this configuration to make sure it suits your requirements.
The frequency of the signal to be measured should be at least twice as fast as the sample clock of your AI task.
2. You can indeed route the signal to all four tasks at the same time (you can refer to the Device Routes page in MAX to double-check routing restrictions). The sampling will be synchronized provided the four counters are started before the AI task, but the counters will be armed at different times unless you configure an Arm Start Trigger (see page 7-45 of the X Series User Manual). I would consider using the ai/StartTrigger if you wish to do this.
The effect of not arming the counters at the same time would be a different number of periods to average on each counter for the very first sample (assuming averaging is enabled). This might not be a big concern but I just wanted to point it out.
3. The routes are available internal to the board so external routing isn't necessary, you can just specify to use the AI Sample clock for the clock of each counter and the routes will be made for you. If you prefer to export the signal on a PFI line and route it back in on a different PFI line this option is also available to you but shouldn't be necessary.
I hope this helps you get started. I'd make sure to take a look at chapter 7 of the X Series User Manual if you get a chance since it describes how all of the counter configurations work in more detail. If you have any related questions don't hesitate to post back.
Best Regards,
John
Message Edited by John P on 12-01-2009 07:52 PM
John Passiak

Measure separation between two signals that may be coincident

Hi
I need to determine the time period between two pulse signals. I'm going to assume for now that I can get these pulses as TTL.
I was initially drawn to the 'Two-Signal Edge-Separation' method using two counter inputs. However, it's quite possible that the signals would be coincident some of the time. Could anyone please answer the following questions:
If my signals were coincident, would the 'two-signal edge-separation' measurement be armed on the edge of signal 1 (= same time as edge of signal 2) and continue counting until the next edge of signal 2 as shown below? Or is it re-armed on the next edge of signal 1?
Is there any other method I could use to log the time between my two pulses? Either as simultaneous counter outputs or something completely different (non-counter method maybe)?
(Probably not relevant at this stage, but I will be using Measurement Studio to implement this - hardware as yet unselected).
Thanks in advnace for any help.
CAS
Solved!
Go to Solution.

Hi CAS,
The count is not re-armed on the next edge of signal 1 using the two-edge separation mode. Once the counter is armed the first time, it will continue counting until signal 2 is detected.
Alternate Approach 1:
If you want the count to reset on every edge of signal 1, you could configure an edge count task (counting the internal timebase) using signal 1 as the count reset terminal and signal 2 as the sample clock. You still would have uncertainty of which signal is detected first if they occur at precisely the same time, so your measured result might be close to 0, or it might be close to 1 full period of the signal in the case that signal 1 and signal 2 are identical.
If you wanted to remove this uncertainty, you can actually delay signal 2 by enabling the PFI filter for the signal 2 terminal. The original intent of this feature was to be able to add a debounce filter to avoid picking up multiple edges on transitions, but a result of the implementation is that the signal is delayed by some amount of time (between the pulse width guaranteed to pass and the pulse width guaranteed to not pass). The best case scenario would be X Series using the 100 MHz timebase, you would add 10 ns of jitter but you could delay the signal by an arbitrary amount. So, you can add the delay and account for it in your reported values, but you would run into problems if the delay caused signal 2 to occur after the 2nd edge of signal 1 (i.e. if the signals were already close to 1 full period apart). You'd have to have an idea of the maximum frequency of the signals as well as the maximum delay between them to determine if this would work or not.
Alternate Approach 2:
You could use two counters configured as edge count tasks. Count the fastest internal timebase. Sample the first counter off of signal 1, and the second counter off of signal 2. If you arm the counters together and ensure that signal 1 and signal 2 start at the same time, then you can simply subtract your buffered samples of counter 1 from your buffered samples of counter 2 to get an array of differences.
There are a number of other ways you could get similar results, but I think the above 2 suggestions are probably the easiest to implement. Alternate Approach 1 has the advantage of still only requiring 1 counter and you don't have to worry as much with arming the counters and starting the sampling together (which could be a problem with Alternate Approach 2 if signal 1 and signal 2 are free-running).
I would recommend X Series DAQ for this task for the following reasons:
The count reset feature mentioned in Alternate Approach 1 is only currently available on X Series and 2nd Generation cDAQ. It will hopefully be added in the somewhat near future to M Series with a driver update but I can't make any guarantees.
The 100 MHz timebase on X Series gives a 10 ns resolution to your measurement. M Series and cDAQ use an 80 MHz timebase (12.5 ns resolution), and E Series uses a 20 MHz timebase (50 ns resolution).
X Series have the most flexible digital filters on their PFI lines and the PFI filters introduce the lowest jitter (compared to M Series and 660x that is--E Series devices do not have digital filters at all).
You didn't mention what frequency you would be using, but X Series have on-board FIFOs which will help you avoid errors from samples being overwritten if your external frequency is relatively fast.
X Series are priced similarly to their M Series equivalents. All X Series have the same counter features with the lowest cost X Series being the PCIe-6320.
Best Regards,
John Passiak

How do I read 2 counters simultaneously using a PXI-6052E board?

Labview help files seem to suggest that I should be able to use the "Group Config" vi to configure 2 counters within a single task ID so that I can read both counters simultaneously with a single read command, but I am having trouble doing this so far.
The only way that I can read both counters is to run the group config vi two times, creating two separate task IDs. For each task ID, I can then run "Set Attribute" to set the attributes of the counters, and then "Get Attribute" to actually read the counter values.
I need to configure the two counters separately (so that each looks at a different input), but I would like to be able to arm them and reset them together.
Any help would be greatly appreciated! I've seen example vis that read them sequentially (in the way that I am doing now), but Labview help suggests that the "Group Config" vi can allow you to group several counters together so that you can address multiple counters with a single read command.
Polly

Hello Polly. Thank you for contacting National Instruments. If you right click on Group Config.vi and select Help, LabVIEW Help will open up. The description of the VI says, "Groups with multiple counters are not currently supported by MIO-16, E Series boards or NI-TIO-based devices." Some legacy boards that we don't sell anymore used to support this, but most of our current boards do not. The best way to do what you want is to configure one counter and then just copy and paste it to make the second one. Please let me know if you have any questions. Have a great day!
Marni S.
National Instruments

6602 Arm Trigger to Sync Multiple Tasks

I am using a 6602 card to read the period of multiple TTL square waves. I am doing this through Matlab using the DAQmx functions. I was able to read the period on one channel perfectly fine.
To check the robustness of the code, I tried reading the same TTL wave through two different counters. The counters were put into seperate tasks, therefore using two StartTask functions. i noticed this caused the tasks to be offset by 15 or so samples.
I believe I should be using an arm trigger to sync the two tasks. I cannot find an arm trigger function for a 6602 to use in Matlab,though. Is there an arm function or should I take another route?

Thanks for the response Gerardo,
I am now collecting the samples continuously. This yielded simultaneously running tasks that are just delayed from one another (which is almost what I want). I was running finite before, but am no longer.
I tried using DAQmxCfgDigEdgeStartTrig but was not successful. I've attached my Matlab code (as a .txt) with the attempted trigger is clearly labeled. I was trying to run an internal trigger or sorts. I am probably way off on this assumption, though. I was thinking I could generate a pulse signal to counter2 and use that as the trigger signal. How wrong is that?
-Mike
Attachments:
contper.txt ‏4 KB

Adjust Counter Delay on the fly using two Counters

Hi,
I'm using the technique described here by JohnP to implement an on the fly delayed output of a hardware counter relative to it's trigger.
http://forums.ni.com/t5/Multifunction-DAQ/Synching-AO-and-Counter-Output-arming-and-triggering-seque...
My system generates a hardware buffered regenerative analog output. A continuous synch pulse is generated using Cntr0 on the same PCI-6221 and is triggered off of the AO.StartTrigger in order to synchronize the Cntr0 Pulse with each generation of the AO wavefrom. Then Cntr1 is configured in retriggerable single sample high/low time mode and triggered off of the Cntr0.InternalOuput. By changing the low time of Cntr1 I can effectively implement an adjustable on the fly delay on the ouput of Cntr1 relative to Cntr0 and hence relative to the AO waveform.
The technique works great for rational values of drive period, (i.e. 1.258 s), but when an irrational waveform period is commanded such as (0.59405940594059405940594059405941 s) the Cntr1 delayed pulse drifts relative to Cntr0. Meaning if you start with a 0 second delay between the two counters, the output pulses are initially aligned but then Cntr1's output will rapidly drift such that the two counter outputs are no longer synchronized.
Clearly there is a rounding error occuring but I can't seem to correct it. I changed the Cntr1 high/low mode from time in seconds to clock ticks thinking I'd have better resolution but still see the same drift with irrational drive periods. I also suspect that by calling the Cntr1 property Cntr.RdyForNewVal in a loop the hardware determinism of my system is compromised.
Our current solution is to simply coherce the user commanded AO drive period to rational values.
I'm mainly wondering if this problem can be corrected or if it's just a limitation of the method using two counters to create an on the fly counter output delay.
Thanks,
Steve

John,
I'm measuring the drift of the output signals (AO and Cntr1) on a daq board scanning at 5000 scans/s.
The information you provided is helpful, I wasn't aware of the divide-down on the internal timebases. Yes, I am specifying the frequency directly to Cntr0 so this may be coerced differently than the AO.
Where does one find these specifics on the board and various clocks?
I've attached some sample code that may be of help to future users of this technique. The sample code outputs a continuous regenerative buffered Analog Output waveform (board hardware timed). Cntr1 is then configured in Frequency mode and triggers off of the AO.StartTrigger in order to synch the two signals. Then Cntr1 is configured in High/Low mode and triggered off of the Cntr0.InternalOutput. By changing the Cntr1 low time, I'm able to get an on the fly delayed output of Cntr1 relative to Cntr0 and hence the AO.
If you have a daq board and you wire the AO and Cntr1 output signals into two analog input signals, you can see the drift when using irrational frequencies. The sample code I provided only performs the output, so to see the signals you can simply create a continuous acquisition task in Max at 5Khz.
Thanks for you time and support.
Attachments:
Delayed Counter Pulse.zip ‏137 KB

6601 CTR/TMR - problem reading multiple counters

I'm developing some code for frequency measurement in Visual C++ using the
NI 6601 counter/timer board. I am able to successfully read the counter
for a single counter; however, my application requires reading multiple counters.
I have code to the effect as follows:
do
nStatus = GPCTR_Watch( nDevice, ulCounter1, ND_ARMED, &ulArmed1 );
nRetVal = NIDAQYield( nYieldOn );
} while ( ( ulArmed1 == ND_YES ) && ( nStatus == 0 ) );
do
nStatus = GPCTR_Watch( nDevice, ulCounter2, ND_ARMED, &ulArmed2 );
nRetVal = NIDAQYield( nYieldOn );
} while ( ( ulArmed2 == ND_YES ) && ( nStatus == 0 ) );
do
nStatus = GPCTR_Watch( nDevice, ulCounter3, ND_ARMED, &ulArmed3 );
nRet
Val = NIDAQYield( nYieldOn );
} while ( ( ulArmed3 == ND_YES ) && ( nStatus == 0 ) );
I have tried a single do..while, but to no avail. In the above code, the
first counter returns, but the next one just hangs there indefinately - not
arming.
Can anyone point me in the right direction on how to read multiple counters
on the 6601?
Thanks,
Aaron Lukacsko
[email protected]

Your program is hanging because you are setup for a continuos read, which means your counter will never unarm. If the first counter never unarms, then your program will hang until the first counter is stopped. You need to either use one Do statement for all for of the GPCTR_Watches or use the Buffer Functions. If you want a continuos buffered operation then you need to use GPCTR_Config_Buffer and GPCTR_Read_Buffer functions. However, if you are just doing a finite number of counts then you use the GPCTR_Watch function, without any buffer functions.
Kevin Bisking
National Instruments
www.ni.com/ask

Arm start trigger

I got two NI 6221 DAQ cards (M-series), each of which has two counters. I want to take the readings from three counters and sychronize them.
Here, I attached the vi that I am using. The problem is that how I can get the arm start trigger? It is stated that the arm start trigger would be better used to sychronize three signals. Could I use vi to generate start trigger sources? Comments are greatly appreciated! Could I use functino generator to simulate the trigger source? Thank you very much in advanced!
Attachments:
sz.vi ‏180 KB

Hi Mayasong,
In this example, the arm start trigger is setup to check for a rising or falling edge on a specified I/O line - labelled trigger source. This will synchronize the counters, and they will start counting when the start trigger condition is met.
What event exactly do you want to start the counter acquisition on? Something from within software, or a hardware event?
If you'd like to synchronize from with a VI, you could write code (eg a function generator) to generate this pulse on an output line, then loop that back into the input you select to arm the trigger. Alternatively, you can do this with a RTSI cable connected between the two cards inside your PC.
This link (below) may help you with synchronization:
http://zone.ni.com/devzone/conceptd.nsf/webmain/6DC991028566309886256F990080A720
Hope this helps!
Mark
Applications Engineer
National Instruments

ACE 4710 one-arm L4 load balancing removes accept-encoding?

We have built a simple one-arm PAT config to round robin load balance two Varnish servers. In the "Default L7 load-balancing action" we have left compression to "N/A". It looks like the ACE removes "Accept-Encoding: gzip, deflate" from the client header.
Is this normal behaviour? We would like the Varnish to do the compression. Do we need modify the headers to get this through the ACE?

Hi,
Yes this does seem to be the behavior. Please read below:
HTTP compression is a capability built into web servers and web browsers to improve site performance by reducing the amount of time required to transfer data between the server and the client. Performing compression on the ACE offloads that work from the server, thereby freeing up the server to provide other services to clients and helping to maintain fast server response times.
When you enable HTTP compression on the ACE, the appliance overwrites the client request with "Accept-Encoding identity" and turns off compression on the server-side connection. HTTP compression reduces the bandwidth associated with a web content transfer from the ACE to the client.
So ACE rewrites the ACCEPT-ENCODING header to IDENTITY to indicate to the server that it should not compress the return data. That would be done by ACE.
Also, default method is used when client comes with both gzip or deflate for "ACCEPT ENCODING". For compression to work, a client must send a request with an ACCEPT-ENCODING method of gzip or deflate. If a client sends both methods, then the ACE uses the configured method(default method).
Also, you can see if ACE is compressing the packets or in "show service-policy detail.
switch/Admin#
show service-policy L7_COMP_SLB_POLICY detail
Status     : ACTIVE
Description: -----------------------------------------
Interface: vlan 1 108
service-policy: L7_COMP_SLB_POLICY
    class: vip
     VIP Address:    Protocol: Port:
     2.0.5.1         tcp        eq    80
      loadbalance:
        L7 loadbalance policy: pm
        VIP ICMP Reply       : ENABLED
        VIP state: OUTOFSERVICE
        Persistence Rebalance: ENABLED
        curr conns       : 0         , hit count        : 0
        dropped conns    : 0
        client pkt count : 0         , client byte count: 0
        server pkt count : 0         , server byte count: 0
        conn-rate-limit      : 0         , drop-count : 0
        bandwidth-rate-limit : 0         , drop-count : 0
        L7 Loadbalance policy : pm
          class/match : h
            ssl-proxy client : c
            LB action :
               primary serverfarm: sf1
                    state: DOWN
                backup serverfarm : -
            hit count        : 0
            dropped conns    : 0
            compression      : on <------------------------------ Compression is enabled if the value is "on"
compression bytes_in : 0       bytes_out : 0 <--- Number of bytes transmitted after compressing the server response
Compression ratio : 0.00% <------------------------------ Percentage of data compressed
Gzip: 0               Deflate: 0 <--------------- Number of times the method is used
compression errors:                                     _
User-Agent : 0               Accept-Encoding    : 0   |
Content size: 0               Content type       : 0   |
Not HTTP 1.1: 0               HTTP response error: 0   |-- Check these error counters to see if they are increasing
Let me know if you have any questions.
Regards,
Kanwal

How do you use the counters on board

I am involved in the development of a LabVIEW VI for the acquisition and processing of signals generated by a chip under test; my application provides two signals having the waveforms sketched in the attached figure.
With reference to this figure, I should generate a digital pulse just after a pulse on signal 1, also in case of no pulses on signal 2.
I am using the board PCI 6110 with LabVIEW 6i: I tryed to use the counters implemented on the board to generate my signal. My idea is to count the pulses of signal 1 with a counter and, if it is possible, to reset the counter on a rising edge of the signal 2. By so doing, when the counter assumes the value “2”, it must generate an impulse. Unfortunately I have not su
cceeded to implement this procedure.
Please, could you suggest me how to implement this solution, or, if this is not possible, any other procedure to accomplish the required task?
Thank you very much for your attention.
Attachments:
figure.jpg ‏17 KB

Hello Gian,
I've tried to think of a method to implement this for a while, but the one fundamental obstacle I keep coming across is that it seems the system must have a deterministic output. (It has to identify the gaps and generate the pulse while on the fly.) It is easy to acquire the two signals and even determining when the gaps occur. The problem is getting your software to recognize this and generate the output fast enough. You could possibly do this with a LabVIEW RT system.
On the other hand, I have thought of a way you could do this with a 660x counter/timer board using quadrature encoder position measurement mode. The problem with the 6110 is that it's counter/timers do not support this mode. With the 660x board in encoder position measurement m
ode, you can wire signal 1 to the source (which increments the counter) and signal 2 to the z-index (which resets the counter to a specified value). You would have this specified value set to be 2 less than the terminal count. If you recieved two signal 1 pulses without any signal 2 pulses, the counter would reach terminal count which triggers a short pulse to be generated on the output and this could be your output signal.
If you do decide to go this route, our technical support can assist you further with this after you have the hardware.
I hope this helps.
Russell
Applications Engineer
National Instruments
http://www.ni.com/support

How do I use AI triggers and counters in DAQ6020-E using LabVIEW 6.0

Hi:
I am new to LabVIEW and sorry for newbie questions. My questions are:
1. I want to use the 2 counters in DAQ6020-E to generate 2 continuous pulse trains(C1 and C2) at different frequencies(C1 @ 1k Hz and C2 @ 2k Hz)and I want to synchronize these 2(for example,they both start with positive edges), how can I accomplish that? should I use a software trigger or a hardware pulse trigger?
2. Followed from 1),there will also be 4 analog inputs(a0,a1,a2,a3) in the same VI. I want them to be triggered by two non-overlapping clock sigals phiA and phiB. phiA and phiB are created by C1 and C2, they both will have 25% duty cycle(with 1k Hz frequency) and are out of phase by 180 degree(thus they wont be bo
th high at the same time).I want a0 triggered by the postive edge of phiA, wait for 0.1 ms, take 1 sample,stop and wait for the next postive edge of phiA. Similarly, a1 will be triggered by negative edge of phiA(wait .1 ms and then sample), a2 by positive edge of phiB, and a3 by negative edge of phiB.
I want to know what pins in the 68-pin connectors corresponding to counter0 and counter1 output, and where should I hook up the triggering phiA and phiB to. Should I initialize them first in Measurement & Automation Explorer?
Thanks so much.
Alan

Hello Alan,
Thank you for contacting National Instruments.
Here are some answers to your questions:
1. You will want to use a harware pulse trigger. This pulse will be connected to the gate of both counters. When a rising edge is detected, both pulse trains will be output on the output pins of the counters. See example attached below.
2. It will not be possible for you to accomplish what you are asking with a DAQPad-6020E. E Series devices only have one analog-to-digital converter (ADC). This means that all 16 channels are multiplexed to a single ADC. This means that it will not be possible to sample(trigger) a0, a1, a2, and a3 simultaneously nor independently. Also, it is not possible to implement the 0.1ms delay from when the edg
e of the sample clock is detected. Here what you can accomplish:
1. You can use an external clock to sample(trigger)a single channel.
2. You can select if you would like the sample your signal on the rising or falling edge of your external clock(phiX).
3. You can use the output of one of the counters as your external sample clock.
I have attached two examples below. One of them generates a pulse train from counter 0. The other acquires analog data from channel 0 by using an external clock.
Here is a link to the DAQPad-6020E User Manual. The output pins for the counter can be found on pages 4-2 and 4-3: http://digital.ni.com/manuals.nsf/websearch/9B5442F668EB7C6B8625669F00743D24?OpenDocument&node=132100_US
Regards,
Bill B.
Applications Engineer
National Instruments
Attachments:
Generate_Pulse_Train_(DAQ-STC).vi ‏103 KB
Cont_Acq&Graph_ExtScanClk.vi ‏108 KB

160 counters in FPGA. Use arrays or 160 loops?

I need to program a 7811R FPGA module to give me 160, 16 bit counters. Originally I made 4 loops (one for each connector) and put the counts from each loop in a 40 element array - mostly to make it easier to program. I'm wondering if that's a bad idea. Would it be better to use an individual loop for each counter? Or maybe use one array per 8 bit port (20, eight element arrays)? I don't have my board yet so I haven't been able to test it.
George

Hello George!
I am terribly sorry I misread your previous question. You want to check for pulses on 160 lines and then keep track of the number of pulses in a 160 element array. I believe this is the only efficent way todo this but I am concerned whether their will be enough real estate on the FPGA to handle this 160 element array. Additionally, its going to take some time to read and process 160 lines at the same time. Therefore you may want to break this up into 20 loops of 8 lines so that you are not waiting for one loop todo all the processing. This would also give you 8 arrays of 20 elements. Sorry it took me so long to get on the same page with this issue. I hope this helps and please continue to write if you have more questions.
Allan S.
National Instruments

My iPad mini won't work at room temperature. I have to warm it up in my hands/arms for 2-3 minutes before the screen works correctly. Anyone else have this issue or know a solution?

Two or three weeks ago, I had a cracked screen replaced on my iPad Mini 2 with retina display (32G). It worked perfectly for 2-3 weeks, so I don't know how relevant the screen repair is. Anyway, the iPad is currently running iOS 8.1.3. I completely reset it because I want to sell it, but recently, the screen display started to have issues. One afternoon I turned it on and the screen was a faint gray with vertical streaks that went away after I turned it off then back on. That night, the screen would stay black when I tried to turn it on. It was a different black to being off, though. When I try to turn it on it changes to a brighter black, if that makes sense. I can see a change in the shade of black, but there's no color or app icons. The sound works even when the screen doesn't. The only way I can get it to turn on properly is if I hold it in my hands/arms for 2-3 minutes. I think the heat from my hands has something to do with it. It's just weird that regular room temperature seems to be too cold. We've had a cold winter in NY this year and my iPad may have spent 1-2 hours in my cold car the day this happened, but I can't say for sure. Has anyone else heard of this issue or does anyone have a solution?

I Also have this problem!!
In my situation, the screen simply started exhibiting the same symptoms a few weeks ago (early February) for no apparent reason. At first I thought the screen was dead, but discovered the heat solution by accident. Now I turn it on and keep it from going to sleep until I go to bed. Thank goodness the battery is still awesome on this thing.
I bought it new and still has the original screen, I keep it at home (never below 62 degrees). Coincidentally, this happened a day or two after the expiration of the warranty!! Any help figuring this one out would be eternally appreciated.
iPad mini retina Wi-Fi, iOS 8.1.3

Simuntaneous arming of counters

Similar Messages

Maybe you are looking for