Sun Fire V250 Error while booting

Question

Dear all,
I have one Sun Fire V250 which was down for fews days and when I booted now it gives the following messages after booting. Is it the problem with the memory modules. It has 2 DIMM with each of 1 GB.
Thanks in Advance
sc>+
sc> poweron+
SC Alert: Host System has Reset+
sc> con+
Invalid command.  Type 'help' for list of commands.+
sc> console+
Enter #. to return to ALOM.+
*1>Init CPU*
+*1>     UltraSPARC[TM] IIIi, Version 2.4*+
*1>DMMU*
*1>DMMU TLB DATA RAM Access*
*1>DMMU TLB TAGS Access*
*1>IMMU Registers Access*
*1>IMMU TLB DATA RAM Access*
*1>IMMU TLB TAGS Access*
*1>Init mmu regs*
*1>Setup L2 Cache*
*1>L2 Cache Control = 00000000.00f04400*
*1>     Size = 00000000.00100000...*
*1>Scrub and Setup L2 Cache*
*1>Setup and Enable DMMU*
*1>Setup DMMU Miss Handler*
*1>Test and Init Temp Mailbox*
*1>CPU Tick and Tick Compare Registers Test*
*1>CPU Stick and Stick Compare Registers Test*
*1>Setup Int Handlers*
*0>Setup Int Handlers*
*0>Send Int CPU 1*
*1>Send Int to Master CPU*
*0>Initialize I2C Controller*
*0>MB:     Part-Dash-Rev#:  3753130-02-50     Serial#:  020322*
*0>Set CPU/System Speed*
*0>MCR Timing index = 00000000.00000002*
*0>..*
*0>Send MC Timing CPU 1*
*0>Probe Dimms*
*1>Probe Dimms*
*1>Init Mem Controller Regs*
*0>Init Mem Controller Regs*
*1>Set JBUS config reg*
*0>Set JBUS config reg*
*0>IO-Bridge unit 0 init test*
*0>IO-Bridge unit 1 init test*
*0>Do PLL reset*
*0>Setting timing to 8:1 10:1, system frequency 160 MHz, CPU frequency 1280 MHz*
*0>Soft Power-on RST thru SW*
*0>CPUs present in system: 0 1*
+*0>*+
*0>Resume selftest...*
*0>Init SB*
*0>Init CPU*
*0>Init mmu regs*
*0>Setup L2 Cache*
*0>L2 Cache Control = 00000000.00f04400*
*0>     Size = 00000000.00100000...*
*0>Setup and Enable DMMU*
*0>Setup DMMU Miss Handler*
*0>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
+*0>     UltraSPARC[TM] IIIi, Version 2.4*+
*1>Init CPU*
+*1>     UltraSPARC[TM] IIIi, Version 2.4*+
*1>Init mmu regs*
*1>Setup L2 Cache*
*1>L2 Cache Control = 00000000.00f04400*
*1>     Size = 00000000.00100000...*
*1>Setup and Enable DMMU*
*1>Setup DMMU Miss Handler*
*1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
*0>Initialize I2C Controller*
*1>Init Mem Controller Sequence*
*0>Init Mem Controller Sequence*
*0>IO-Bridge unit 0 init test*
*0>IO-Bridge unit 1 init test*
*0>Select Bank Config*
*0>Probe and Setup Memory*
*0>INFO:     1024MB Bank 0, Dimm Type X4*
*0>INFO:     1024MB Bank 1, Dimm Type X4*
*0>INFO:     No memory detected in Bank 2*
*0>INFO:     No memory detected in Bank 3*
+*0>*+
*0>Data Bitwalk on Master*
*0>     Test Bank 0.*
+*0>*+
*0>ERROR: TEST = Data Bitwalk on Master*
*0>H/W under test = CPU0: Bank0 DIMM0, Motherboard*
*0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
*0>MSG = Pin 79 failed on CPU0: Bank0 DIMM0, Motherboard*
*0>END_ERROR*
*0>     Test Bank 1.*
+*0>*+
*0>ERROR: TEST = Data Bitwalk on Master*
*0>H/W under test = CPU0: Bank1 DIMM0, Motherboard*
*0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
*0>MSG = Pin 79 failed on CPU0: Bank1 DIMM0, Motherboard*
*0>END_ERROR*
+*0>*+
*0>ERROR: TEST = Data Bitwalk on Master*
*0>H/W under test = CPU, Memory, Motherboard*
*0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
*0>MSG =*
*      *** Test Failed!! ****
*0>END_ERROR*
+*0>*+
*0>ERROR: TEST = Data Bitwalk on Master*
*0>H/W under test = CPU, Memory, Motherboard*
*0>Repair Instructions: Replace items in order listed by 'H/W under test' above*
*0>MSG = No good memory available on master CPU 0, rolling over to new Master.*
*0>END_ERROR*
*1>Soft Power-on RST thru SW*
*1>CPUs present in system: 0 1*
*1>OBP->POST Call with %o0=00000000.05002000.*
*1>Diag level set to MIN.*
*1>MFG scrpt mode set to NONE*
*1>I/O port set to TTYA.*
+*1>*+
*1>Start selftest...*
*1>Init SB*
*1>Init CPU*
*1>DMMU*
*1>DMMU TLB DATA RAM Access*
*1>DMMU TLB TAGS Access*
*1>IMMU Registers Access*
*1>IMMU TLB DATA RAM Access*
*1>IMMU TLB TAGS Access*
*1>Init mmu regs*
*1>Setup L2 Cache*
*1>L2 Cache Control = 00000000.00f04400*
*1>     Size = 00000000.00100000...*
*1>Scrub and Setup L2 Cache*
*1>Setup and Enable DMMU*
*1>Setup DMMU Miss Handler*
*1>Test and Init Temp Mailbox*
*1>CPU Tick and Tick Compare Registers Test*
*1>CPU Stick and Stick Compare Registers Test*
*1>Set Timing*
+*1>     UltraSPARC[TM] IIIi, Version 2.4*+
*0>Init CPU*
+*0>     UltraSPARC[TM] IIIi, Version 2.4*+
*0>DMMU*
*0>DMMU TLB DATA RAM Access*
*0>DMMU TLB TAGS Access*
*0>IMMU Registers Access*
*0>IMMU TLB DATA RAM Access*
*0>IMMU TLB TAGS Access*
*0>Init mmu regs*
*0>Setup L2 Cache*
*0>L2 Cache Control = 00000000.00f04400*
*0>     Size = 00000000.00100000...*
*0>Scrub and Setup L2 Cache*
*0>Setup and Enable DMMU*
*0>Setup DMMU Miss Handler*
*0>Test and Init Temp Mailbox*
*0>CPU Tick and Tick Compare Registers Test*
*0>CPU Stick and Stick Compare Registers Test*
*0>Setup Int Handlers*
*1>Setup Int Handlers*
*1>Send Int CPU 0*
*0>Send Int to Master CPU*
*1>Initialize I2C Controller*
*1>MB:     Part-Dash-Rev#:  3753130-02-50     Serial#:  020322*
*1>Set CPU/System Speed*
*1>MCR Timing index = 00000000.00000002*
*1>..*
*1>Send MC Timing CPU 0*
*1>Probe Dimms*
*0>Probe Dimms*
*0>Init Mem Controller Regs*
*1>Init Mem Controller Regs*
*0>Set JBUS config reg*
*1>Set JBUS config reg*
*1>IO-Bridge unit 0 init test*
*1>IO-Bridge unit 1 init test*
*1>Do PLL reset*
*1>Setting timing to 8:1 10:1, system frequency 160 MHz, CPU frequency 1280 MHz*
*1>Soft Power-on RST thru SW*
*1>CPUs present in system: 0 1*
+*1>*+
*1>Resume selftest...*
*1>Init SB*
*1>Init CPU*
*1>Init mmu regs*
*1>Setup L2 Cache*
*1>L2 Cache Control = 00000000.00f04400*
*1>     Size = 00000000.00100000...*
*1>Setup and Enable DMMU*
*1>Setup DMMU Miss Handler*
*1>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
+*1>     UltraSPARC[TM] IIIi, Version 2.4*+
*0>Init CPU*
+*0>     UltraSPARC[TM] IIIi, Version 2.4*+
*0>Init mmu regs*
*0>Setup L2 Cache*
*0>L2 Cache Control = 00000000.00f04400*
*0>     Size = 00000000.00100000...*
*0>Setup and Enable DMMU*
*0>Setup DMMU Miss Handler*
*0>Timing is 8:1 10:1, sys 159 MHz, CPU 1279 MHz, mem 127 MHz.*
*1>Initialize I2C Controller*
*0>Init Mem Controller Sequence*
*1>Init Mem Controller Sequence*
*1>IO-Bridge unit 0 init test*
*1>IO-Bridge unit 1 init test*
*1>Select Bank Config*
*1>Probe and Setup Memory*
*1>INFO: No memory on cpu 1*
+*1>*+
*1>ERROR: TEST = Probe and Setup Memory*
*1>H/W under test = CPU1 Memory*
*1>Repair Instructions: Replace items in order listed by 'H/W under test' above*
*1>MSG = No good memory available on master CPU 1, rolling over to new Master.*
*1>END_ERROR*
*1>ERROR:*
*1>     POST toplevel status has the following failures:*
*1>          CPU0: Bank0 DIMM0, Motherboard*
*1>          CPU0: Bank1 DIMM0, Motherboard*
*1>END_ERROR*
+*1>*+
*1>ERROR:     No good CPUs OR CPUs with good memory left.  Calling debug menu.*
*1>     0     Peek/Poke interface*
*1>     1     Dump CPU Regs*
*1>     2     Dump Mem Controller Regs*
*1>     3     Dump Valid DMMU entries*
*1>     4     Dump IMMU entries*
*1>     5     Dump Mailbox*
*1>     6     Dump IO-Bridge regs unit 0*
*1>     7     Dump IO-Bridge regs unit 1*
*1>     8     Allow other CPUs to print*
*1>     9     Do soft reset*
*1>     ?     Help*

Answer 1

I have just experienced this issue while patching Solaris 10 on a V240 system using Live Upgrade.
The issue was resolved by performing a failsafe boot from the console ("boot -F failsafe"), splitting the (new/alt) root mirror, mounting the primary half, performing fsck several times (as filesystem issues were apparrent), then mounting the slice and installing the new bootblock using the version of installboot from the new root and rebuilding the boot archive manually:
# mount /dev/dsk/c1t0d0s4 /a
#  /a/usr/sbin/installboot /a/usr/platform/`uname -i`/lib/fs/ufs/bootblk /dev/rdsk/c1t0d0s4
# bootadm update-archive -R /aI note that the OpenSolaris bug linked to above lists four criteria for reproducing this problem:
1. Install u6 ( SUNWCreq ( no mkisofs so we build ufs boot archive )
2. Limit /tmp to 512M ( so forcing the ufs build to happen in /var/run
3. Have seperate /var ( bootadm.c only lofs nosub mounts / when creating the alt root for DAP patching build of boot archive )
4. Install 139555-08
The system I was patching met the last three of these, but not the first one (pkginfo does not show SUNWCreq as being installed). However, this was not an OpenSolaris system, which may make a difference.
Rob