Synchronization - Master and Slave tasks.

For syncrhonisation (via hardware) of two modlues; one 4330 and 6361, shall I create one master task for the 4330 and then syncrhinise it with the 6361 module? Or create multiple channels say 5 from 4330 and 5 from 6361 and then specify one channel from 4330 to be the master and all the rest modules from 4330 and 6361 to be slave tasks?
Thanks,

Hi Pepis21,
My name is George and I am an Applications Engineer at National Instruments. I see Luke has already done a good job of helping you but I found a couple of examples that you might find helpful.
Here is a tutorial that shows a few more examples of how to synchronise channels and devices using a couple of different methods;
http://www.ni.com/tutorial/11549/en/
You may be able to see some other synchronisation examples in the NI example finder within LabVIEW under “DAQmx” under “Hardware Input and Output”. I will also link an image of another example below that shows how to use error wires to force dataflow without using flat sequence structures as Luke suggested.
I hope these are useful for you.
Regards,
George

Similar Messages

Master and Slave concept

hi guys,
i am confused about the master and slave realtionship in ospf. any one can explain it to me in detail.

Hello Pankaj,
The Master and Slave in OSPF are a slightly confusing concept but the idea behind it is quite simple.
When two routers decide to become fully adjacent, they must synchronize their LSDBs. OSPF tries to optimize this: the routers first exchange only the list of entries in their LSDBs. Each router compares the received list to the list of items in its own database, and if it finds that an LSA is missing or is older than one the neighbor knows about, it requests it from the neighbor afterwards. This way, both routers transmit only the missing or updated LSAs, not the entire LSDBs.
The list of LSDB entries is carried in Database Description (DBD) packets. Naturally, when routers exchange DBD packets, they must be sure all of them have been properly received by the neighbor, so some sort of acknowledgements must be used. There is a problem here, however: the only packets in OSPF used to carry acknowledgements are LSAck packets, but they can only be used to acknowledge LSU packets (more precisely, individual LSAs carried in LSU packets), not DBD packets. How shall the acknowledgements of DBD packets be accomplished, then?
OSPF uses a polling style of communication with the DBD packets. DBD packets themselves have sequence numbers used for sequencing and acknowledgement purposes. One of the two routers that are in the synchronization phase will be the one responsible for polling the other (i.e. calling it out it to send another piece of information if it has any), each time with an incremented sequence number. This is the Master role. The other router will only be allowed to respond to a DBD poll, never send any DBD packet without being polled immediately before, and the response DBD packet must carry the sequence number of the Master's DBD poll packet. This is the Slave role. The Slave must respond to each Master's DBD packet even if it has no more LSDB entries to advertise; in that case, the DBD response body will be empty.
So during the DBD exchange, the Master sends DBD packets to Slave, incrementing the sequence number by one in each round. The Slave waits for DBD packets from the Master and only responds to them, and each response carries the sequence number from the last received Master's DBD packet that was used to poll the Slave. Remember: a Slave must not send DBD packets on its own, only as responses to DBD packets received from the Master, and the sequence number of the Slave's response DBD packet must be set to the Master's poll DBD packet.
While I call the DBD packets as "polls" and "responses" here for the sake of clarity, the DBD packets do not have this distinction indicated explicitly. Any DBD packet sent from the Master, either with a body carrying a list of LSAs or an empty body, is a poll. Any DBD packet sent from the Slave, again either with a non-empty or empty body, is a response. A DBD packet can have an empty body if the router needs to send a DBD packet to the neighbor (either from Master to repeatedly poll the Slave, or from the Slave to confirm the arrival of the DBD packet from the Master) but has no more LSDB entries to advertise itself.
There are two issues with this simple procedure. First, there is the issue of who out of two synchronizing routers will be the Master and who will be the Slave. This is resolved during the ExStart phase: both routers initially treat themselves as Master routers, and send DBD packets with random initial sequence numbers to each other, indicating the MS flag (Master) in their header. As they do this, the router with the lower RouterID moves to the Slave role, while the router with the higher RouterID remains in the Master role. The ExStart phase is basically finished after establishing the router's role in the synchronizing pair; at most two DBD packets are needed for that, one from each router. The Exchange phase then lasts until routers have exchanged the entire list of their LSDB entries using DBD packets.
The second issue is more subtle: how should the Master know whether the Slave needs to be polled further? Clearly, a situation may arise when the Master's LSDB is empty or smaller than the Slave's, and the Master will need to send fewer DBDs than the Slave to list all its LSDB contents. As the Slave can not send a DBD packet on its own, it somehow needs to tell the Master to poll it again. This is accomplished by another flag in DBD packet header, the M (More) flag. If a Slave replies to the Master's DBD packet with its own DBD packet and the M flag set, the Master knows the Slave needs to be polled again. The Master will stop polling the Slave after the last DBD packet fom the Slave has the M flag cleared.
The RFC 2328 has a nice ASCIIart graph of the adjacency coming up:
            +---+                                         +---+
            |RT1|                                         |RT2|
            +---+                                         +---+
            Down                                          Down
                            Hello(DR=0,seen=0)
                       ------------------------------>
                         Hello (DR=RT2,seen=RT1,...)      Init
                       <------------------------------
            ExStart        D-D (Seq=x,I,M,Master)
                       ------------------------------>
                           D-D (Seq=y,I,M,Master)         ExStart
                       <------------------------------
            Exchange       D-D (Seq=y,M,Slave)
                       ------------------------------>
                           D-D (Seq=y+1,M,Master)         Exchange
                       <------------------------------
                           D-D (Seq=y+1,M,Slave)
                       ------------------------------>
                           D-D (Seq=y+n, Master)
                       <------------------------------
                           D-D (Seq=y+n, Slave)
             Loading   ------------------------------>
                                 LS Request                Full
                       ------------------------------>
                                 LS Update
                       <------------------------------
                                 LS Request
                       ------------------------------>
                                 LS Update
                       <------------------------------
             Full
The I flag here is another flag in DBD headers called the Init flag, and is set only on initial DBD packets in the ExStart phase. If the router has established its Master or Slave role, it clears the I flag. This one is not really that important right now.
The Master/Slave relationship is built and relevant only during the initial LSDB synchronization when a new adjacency is being established. After the two routers go past the Exchange state, DBD packets are not used anymore, and the whole Master/Slave relationship is forgotten. Remember: Master/Slave is relevant only to DBD packets, and DBD packets are used only in ExStart/Exchange phases. Outside of these states, there are no DBD packets used, hence no Master/Slave relationships exist.
If there are, say, four routers, R1 till R4, connected to the same switch and run OSPF, during the OSPF bootup, there will be 5 temporary Master/Slave relationship built and torn down afterwards:
between the DR and BDR as they synchronize (assume those routers are R1 and R2)
between R3 and DR
between R3 and BDR
between R4 and DR
between R4 and BDR
Notice the Master/Slave relationship existed between those routers that went through ExStart and Exchange into the Full state. Also keep in mind that in the Full state, there are no more Master/Slave relationship present - they were only needed because of the specific needs of the DBD packet exchange.
Does this make the issue a little more clear? Please feel welcome to ask further!
Best regards,
Peter

Master and Slave Loops

I'm having problems with my Master and slave loop combination. I would like to be able to start and stop acquiring data from individual thermocouples. Please help.
Message Edited by nicholas03 on 04-13-2008 03:22 PM
Attachments:
eight thermo.JPG ‏106 KB

Dear Nicholas,
My first advise would be to check the examples on master-slave patterns, and run them step by step, looking at what the data does...
In a master-slave system, you use the queue to pass data from the master to the slave.   You're not passing data in the queue... in stead, you're passing data using local variables, which you should NOT do...
In the top loops, you should attach the temp array to the enqueue element.   In the bottom loop, you should remove the temp local, and instead get your data from the dequeue vi.
Also, you have to create a queue with the proper variable.   You can create a queue from any variable type, but it has to know beforehand, and the init vi.
Assuming you want to queue the temp array, you're basic structure should look like this:
It does help if you add your own code, so we can easier edit it for you... Otherwise we need to use photoshop on your design...
Message Edited by Anthony de Vries on 04-14-2008 11:30 AM
Attachments:
master-slave1.JPG ‏24 KB

Master and Slave configurations

Hi
I am currently wondering why my master and slave configurations dan't work. I have the Rev. B mother board and I set the jumpers to the right spots. I am trying to get my CD Burner to work with my regular CD Rom on the same wire.

Jarrett,
my experience with my 3 Beige G#'s (1 desktop and two towers), tells me that a master/slave configuration with two optical drives is not really possible/compatible.
As a matter of fact, I had to opt for the following solution:
- Sony 52X burner installed in the CD bay;
- Iomega 52X USB burner on the USB PCI card.
I also had a huge number of problems with the master/slave configuration of drives, and it only worked with certain brands of drives.
For instance, two WD drives would not get along in the same case (data corruption like there's no tomorrow.....)
I ended up having a WD and a Seagate, which still get a long nowadays in my B&W G3.
To give you some more curious feedback on the bad habits of the Beige machines........my old G3 now sits in my son's room.
Believe it or not, I had to remove the Sony burner, as the computer would not boot from it, at all.
It would read and play CD's but it would not boot, in the most standard of the configurations:
- CD Burner Master and 1 IDE drive as a slave;
- SCSI card with SCSI drive;
I replaced the burner with the APPLE CD-drive form my B&W, and the system started working and booting like magic (I swear....I did not change anything else).
It boils down to trying and experimenting. I spent countless hours with those machines trying to figure out why the same configuration working on my Beige minitower would not work on my daughter's Beige minitower, exactly identical machines, both with rev. B boards.
Hope this can help.
cheers

Master and slave problem

Hi Everyone,
When I try to use the MAster and slave template which is provided by the NI itself, try to understand it how it works, but when I use this concept to implement in my code, just found there is the problem at there:
Problem:
1. The master loop always looping even though there do have a notification from the master to slave but the slave do not respond anything, can't figure the reason.
2. When the master loop is exit then the slave loop just start to execute but it is too late cos master loop already exit.
Those senario are different from the master and slave template. need your help.
Thanks
William Lee

Hi Williamlee,
Thanks for contacting National Instruments,
It would be much easier if we could see your code, this will help us work out where the issue is, and to help us understand where you maybe having issues...
Also I would like to include some more information with regards to the Master/Slave template.Developer Zone article : Application Design Patterns : Master/Slave and also a webcast on Software Design Architectures in NI LabVIEW
Kind regards,
Ashish Naik
Field Sales Engineer
National Instruments UK

Multiple errors with DSC modules modbus master and slave

Hi,
I've searched quite a lot of posts but haven't found solution for my problem. I'm playing with LabVIEW DSC module and it's modbus master and slave functionalities. Even the LabVIEWs own modbus examples (Modbus Simulator and Fundamentals) seem to work randomly or not at all: When checking the Variable Manager utility Modbus Simulator (i.e. modbus slave/server) seems to deploy variables correctly with good quality but Modbus Fundamentals (i.e. modbus master/client) most often shows unknown value or bad quality for all the variables. When running the VIs I get 'Error -1950679035 Unable to locate variable in the Shared Variable Engine' and sometimes some other errors too. If the Modbus Simulator (slave/server) is expected to work fine I guess I should get two slaves communicating, but this isn't happening either. So maybe Modbus Simulator example isn't working either.
I've tried undeploying and deploying the libraries, stopping and starting the SVE, booting PC, reinstalling DSC module, and setting firewall and antivirus software off. This problem is going on with two different computers, both of which have recently installed LabVIEW 2011, first PC with Win XP and second PC with Win 7. No other OPC servers should be installed to these computers. And what is really interesting, the problem seems to have nothing to do with my network since Simulator and Fundamentals examples are not working even if the network cable is unplugged!
Any suggestions? Replies are highly appreciated!

V8 has the same feature, but the words are different.
The Generator typically uses the Driver time base, and the Gl. Var Write is writing once per block.
So, to see all values, you must have a block size of one.
I set up the Driver timebase to 10 Hz, block size of 1. The Generator and the Read Variable default to the Driver timebase.
The Generator is making a 2 Hz Rectangle waveform. YOu can see that it's shifted, but otherwise intact.
- cj
Measurement Computing (MCC) has free technical support. Visit www.mccdaq.com and click on the "Support" tab for all support options, including DASYLab.

DNS addresses (master and slave) + personalizing the url address

Hello.
My name is Fernando and I published my site using MobileMe (www.fernandoingles.com).
It’s working already really well.
But since I’m from Brazil, I built one in Portuguese as well.
And since the common site endings here are .br I’m trying to purchase the www.fernandoingles.com.br as well but in order to be able to actually buy the site I have to give them two DNS addresses of the place I’m publishing the website with.
(one ‘Master’ and one ‘Slave’).
How can I get those addresses?
And another thing is that I also have my bands site’s published under my main domain name (fernandoingles.com) with my main MobileMe account (but I have the family pack now).
[www.pipeusa.net and www.pipebrasil.com]
I purchased those Urls using GoDaddy and they are all properly forwarded already, which means that when the person types those addresses above it already goes to the correct site.
But what shows on the actual url above is (http://www.fernandoingles.com/fernandoingles.com/Pipe.html).
And what I would like to appear is only the addresses (www.pipeusa.net and www.pipebrasil.com) instead of my name before them.
I bought the family pack so that I would have more space and etc... and already put those addresses ((www.pipeusa.net and www.pipebrasil.com and fernandoingles.com.br) as their main domain.
But since I’m publishing them all using my own iWeb how could I make those extra sites work as their own main sites?
Would it work if I log in with the desired MobileMe sub-account (let’s say www.pipeusa.net) and then go to iWeb, move that site to the top and them publish it?

Thank you so much for the response!
Great option on the added accounts!!
Since I manage all those sites myself could I manage them all within the same 'log in' or each and every time I need to make a change on one of those sites I must 'log out' of whatever account I'm in and then 'log in' into the account that the change needs to be made?
And whenever I 'log in' into those accounts (the ones that have the respective domains) should I replace on iWeb before I publish the top site with the one I want to as the main domain or can I just not do anything at all?
And about the DNS address issue,
Since I’m from Brazil, I always build two sites, one in Portuguese and one in English.
And since the common site endings here in Brazil are '.br' I’m trying to purchase the '.br' option of all the addresses I have as well but in order to be able to actually buy the site I have to give them two DNS addresses of the place I’m publishing the website with.
(one ‘Master’ and one ‘Slave’).
How can I get those addresses?"
Thank you so much for the help!!!!

Assign my 2 servers as master and slave driver

I am trying to set up my 2 servers which already have had data and information: one as Master and the other as Slave how to use the unix commands to do this.
Thank you very much,
Paul

Hi Williamlee,
Thanks for contacting National Instruments,
It would be much easier if we could see your code, this will help us work out where the issue is, and to help us understand where you maybe having issues...
Also I would like to include some more information with regards to the Master/Slave template.Developer Zone article : Application Design Patterns : Master/Slave and also a webcast on Software Design Architectures in NI LabVIEW
Kind regards,
Ashish Naik
Field Sales Engineer
National Instruments UK

Syncronization of 2 USRP in Reception (master and slave)

Hi,
When I run "niUSRP EX Rx Finite Sync.vi " for the USRP slave device connected to the master via the MIMO cable. I set:
Reference Frequency Source -> MIMO
Timebase Clock Source -> MIMO
I have the following error "niUSRP Initiate.vi <err> The PLL reference clock About did not lock Within the alloted time"
Can you help to resolve this problem?
Can you help me to synchronize two USRP in reception: one slave and the other is the master connected with MIMO cable?
Thank you
Solved!
Go to Solution.
Attachments:
niUSRP EX Rx Finite Sync.vi ‏32 KB

I set this parameters to the master device that is connected directly to my laptop and10 MHz generator and PPS generator::
IPAdressMaster=192.168.10.2
Reference Frequency Source -> RefIn
Timebase Clock Source -> PpsIn
-----> that's work
However, when i tried with the slave device that is connected to the master via the MIMO cable :
IPAdress=192.168.10.3
Reference Frequency Source -> MIMO
Timebase Clock Source -> MIMO
-----> I have the error mentionned in my first message
Where is the problemem?
this exemple ("niUSRP EX Rx Finite Sync.vi " ) allow us to verify the good working of slave device?
thank you

Synchronize input and output tasks to start at the same sample point [C++ NI_DAQmx Base]

I'm trying to initiate the analog input and output streams to start reliably at the same sample. I've tried triggering the output from the start of the input using the following code [NI-DAQmx Base 2.1 under Mac OS X with an M-Series multifunction board]. It compiles and runs, but gives an error message at the call to "DAQmxBaseCfgDigEdgeStartTrig". Any suggestions about synchronized I/O on this platform?
#include "NIDAQmxBase.h"
#include
#include
#include
#define DAQmxErrorCheck( functionCall ) { if ( DAQmxFailed( error=( functionCall ) ) ) { goto Error; } }
int main( int argc, char *argv[] )
// Task parameters
int32 error = 0;
TaskHandle inputTaskHandle = 0;
TaskHandle outputTaskHandle = 0;
char errorString[ 2048 ] = {'\0'};
int32 i;
time_t startTime;
// input channel parameters
char inputChannelList[] = "Dev1/ai0, Dev1/ai1";
float64 inputVoltageRangeMinimum = -10.0;
float64 inputVoltageRangeMaximum = 10.0;
// output channel parameters
char outputChannelList[] = "Dev1/ao0, Dev1/ao1";
char outputTrigger[] = "Dev1/ai/StartTrigger";
float64 outputVoltageRangeMinimum = -10.0;
float64 outputVoltageRangeMaximum = 10.0;
// Timing parameters
char clockSource[] = "OnboardClock";
uInt64 samplesPerChannel = 100000;
float64 sampleRate = 10000.0;
// Input data parameters
static const uInt32 inputBufferSize = 100;
int16 inputData[ inputBufferSize * 2 ];
int32 pointsToRead = inputBufferSize;
int32 pointsRead;
float64 timeout = 10.0;
int32 totalRead = 0;
// Output data parameters
static const uInt32 outputBufferSize = 1000;
float64 outputData[ outputBufferSize * 2 ];
int32 pointsToWrite = outputBufferSize;
int32 pointsWritten;
for( int i = 0; i < outputBufferSize; i++ )
outputData[ 2 * i ] = 9.95 * sin( 2.0 * 3.14159 * i / outputBufferSize );
outputData[ 2 * i + 1 ] = -9.95 * sin( 2.0 * 3.14159 * i / outputBufferSize );
// ------------------- configure input task -----------------------
DAQmxErrorCheck ( DAQmxBaseCreateTask( "", &inputTaskHandle ) );
printf( "Created input task\n" );
DAQmxErrorCheck ( DAQmxBaseCreateAIVoltageChan( inputTaskHandle, inputChannelList, "", DAQmx_Val_RSE, inputVoltageRangeMinimum, inputVoltageRangeMaximum, DAQmx_Val_Volts, NULL ) );
printf( "Created AI Voltage Chan\n" );
DAQmxErrorCheck ( DAQmxBaseCfgSampClkTiming( inputTaskHandle, clockSource, sampleRate, DAQmx_Val_Rising, DAQmx_Val_ContSamps, samplesPerChannel ) );
printf( "Set sample rate\n" );
// ------------------- configure output task -----------------------
DAQmxErrorCheck ( DAQmxBaseCreateTask( "", &outputTaskHandle ) );
printf( "Created output task\n" );
DAQmxErrorCheck ( DAQmxBaseCreateAOVoltageChan( outputTaskHandle, outputChannelList, "", outputVoltageRangeMinimum, outputVoltageRangeMaximum, DAQmx_Val_Volts, NULL ) );
printf( "Created AO Voltage Chan OK\n" );
DAQmxErrorCheck ( DAQmxBaseCfgSampClkTiming( outputTaskHandle, clockSource, sampleRate, DAQmx_Val_Rising, DAQmx_Val_ContSamps, samplesPerChannel ) );
printf( "Set sample rate\n" );
// trigger output when input starts
DAQmxErrorCheck ( DAQmxBaseCfgDigEdgeStartTrig( outputTaskHandle, outputTrigger, DAQmx_Val_Rising ) );
printf( "Set output trigger\n" );
// ------------------- configuration -----------------------
// write output signal
DAQmxErrorCheck ( DAQmxBaseWriteAnalogF64( outputTaskHandle, pointsToWrite, 0, timeout, DAQmx_Val_GroupByScanNumber, outputData, &pointsWritten, NULL ) );
printf( "Write output signal\n" );
// set up input buffer
DAQmxErrorCheck ( DAQmxBaseCfgInputBuffer( inputTaskHandle, 200000 ) ); // use a 100,000 sample DMA buffer
// initiate acquisition - must start output task first
DAQmxErrorCheck ( DAQmxBaseStartTask( outputTaskHandle ) );
DAQmxErrorCheck ( DAQmxBaseStartTask( inputTaskHandle ) );
// The loop will quit after 10 seconds
Dr John Clements
Lead Programmer
AxoGraph Scientific

Hi Michael,
First of all, thanks very much for taking the time to investigate this problem! Much appreciated.
You asked for "an actual error code you got and any description that is given". The full output from the program that I posted earlier in this thread is appended to the end of this message. In summary, following the call to...
DAQmxErrorCheck ( DAQmxBaseCfgDigEdgeStartTrig( outputTaskHandle, outputTrigger, DAQmx_Val_Rising ) );
... with ...
char outputTrigger[] = "Dev1/ai/StartTrigger";
...the error message is ...
DAQmxBase Error: Specified route cannot be satisfied, because the hardware does not support it.
You asked "specifically which M series device you are using"? It is the PCIe 6251 (with BNC 2111 connector block). I'm testing and developing on an Intel Mac Pro (dual boot OS X and Windows XP).
You asked for "the location you pulled the code from". Here it is...
http://zone.ni.com/devzone/cda/epd/p/id/879
...specifically from the file "Multi-Function-Synch AI-AO_Fn.c".
I adapted the NI-DAQmx calls to their NI-DAQmx Base equivalents.
Finally, you asked "Is the trigger necessary, or do you just need to know that the measurements are running on the same clock?". I believe that some kind of sychronized trigger is necessary in my situation (correct me if I'm wrong). Timing is crucial. Say I initiate an analog output stream that delivers a voltage command step 5 ms from the onset. I need to record the response (analog input stream) so that its onset is accurately aligned (synchronized) at 5 ms. A typical recording situation would stimulate and record a short data 'sweep', then wait for the (biological) system to recover, then stimulate and record another short sweep, and repeat. I need all the recorded sweeps to align accurately so that they can be averaged and analyzed conveniently.
I definitely do not want my customers to rely on an expensive external TTL pulse generator to initiate and synchronize each 'sweep'. That would effectively eliminate the cost advantage of an NI board, as well as adding unnecessary complexity in setup and use. It would be a show-stopper for me.
It seems perverse, but would it be possible to use a digital output channel connected directly to a digital input chanel to trigger the input and output streams?
Regards,
John.
Full output from test program. Compiled with gcc 4 under OS X...
[Session started at 2007-05-23 14:17:01 +1000.]
LoadRuntime: MainBundle
CFBundle 0x303cc0 (executable, loaded)
_CompatibleWithLabVIEWVersion: linkedAgainst: 08208002
_CompatibleWithLabVIEWVersion: result= false, mgErr= 1, theActualVersion= 00000000
_CompatibleWithLabVIEWVersion: linkedAgainst: deadbeef
_CompatibleWithLabVIEWVersion: Reseting Linked Against
_CompatibleWithLabVIEWVersion: linkedAgainst: 08208002
_CompatibleWithLabVIEWVersion: result= true, mgErr= 0, theActualVersion= 00000000
_CompatibleWithLabVIEWVersion: linkedAgainst: 08208002
_CompatibleWithLabVIEWVersion: result= true, mgErr= 0, theActualVersion= 00000000
com.ni.LabVIEW.dll.nidaqmxbaselv
CFBundle 0x313760 (framework, loaded)
{type = 15, string = file://localhost/Library/Frameworks/nidaqmxbaselv.framework/, base = (null)}
Amethyst:Library:Frameworks:nidaqmxbaselv.framework
2007-05-23 14:17:02.248 test-ni[4445] CFLog (21): Error loading /Library/Frameworks/LabVIEW 8.2 Runtime.framework/resource/nitaglv.framework/nitaglv: error code 4, error number 0 (no suitable image found. Did find:
/Library/Frameworks/LabVIEW 8.2 Runtime.framework/resource/nitaglv.framework/nitaglv: mach-o, but wrong architecture)
CFBundle 0x1751fdc0 (framework, not loaded)
Created input task
Created AI Voltage Chan
Set sample rate
Created output task
Created AO Voltage Chan OK
Set sample rate
DAQmxBase Error: Specified route cannot be satisfied, because the hardware does not support it.
test-ni has exited with status 0.
Dr John Clements
Lead Programmer
AxoGraph Scientific

Dual spi device with one master and one slave on the PC end

The powers that be want to emulate a hight speed RS-232 connection to an instrument we are building. We don't want to poll the instrument to see if it has data. They want the instrument to have both master and slave SPI busses so that it can push data to us.
I need to find the PC hardware to do this that is compatable with LabView so I can test it. It doesn't have to be a single device. It could be two as long as one can be master and the other slave. We have the NI USB-8452 but it can't be slave.
TIA Norm
Attachments:
Dual SPI.png ‏26 KB

Hi Viper
You are right, the 8451 can only be configured as an SPI Master. For creating a slave you would have to choose an FPGA based solution. Depending on the hardware from NI that you currently have, you can choose from different FPGA cards or devices. I found some links that might help you with your search:
Community: SPI Slave Device in FPGA
White Paper: Implementing SPI Communication Protocol in LabVIEW FPGA
Forums: Slave SPI product recomendation
Forum: SPI in FPGA Multifunctional card discussion
White Paper: SPI and LV basics (check section 7)
Hope the information provided is helpful.
WenR

How to make one Mac the "master", and the other Macs "secondary"?

When using ISync to my DotMac account, and using three or four Macs all synching to one DotMac account, is it possible to designate one particular Mac to be the "most important" or "parent" Mac, and then all others, (laptops), be less important?
I just want the Address Book on the main machine, the G5 Desktop, to always take precedence, and never get overwritten in any way, by a less refined Address Book on a laptop traveling machine.
Thank you.

iSync (or rather .Mac Sync is what you are referring to) does not work like that.
There is no master and slave relationship in synchronising. All devices are equal and all devices sync their data to all other devices equally. That is what true synchronising is.
What you are proposing is not synchronising - it is a simple copy and replace operation from one source, and the SyncServices framework is not designed for that.
The whole point of synchronising is to get away from having a Master data source. You can change data on ANY device (Mac, phone or PDA) and the changes will be synced to all other devices.

Synchronizing AI and Counter Tasks in DSA and M Series devices

Hello DAQ fellows, I am new in the Counter field, so it would be really helpful to have your comments and advices about my application.
I need to acquire simultaneouslythe following signals:
- AI Voltage signal with a DSA device (PXI 4461).
- AI voltage signal with a M Series device (PXI 6250).
- Periods between TTL pulses signal with one counter of the same M Series device. I want to use the counter as it is shown in the figure 7-8 attached below.
You can see my approach in the vi attached below (4461-6250ai-6250Ctr.vi). The 4461 is the master device.
For the synchronization between both AI tasks I am using the "SampleClockTimebase" of the master device as a source for the 6250. I am also using the "StartTrigger" signal from the master device to trigger the start of the AI acquisition in the 6250. As I understand, this configuration is OK.
Now come the second stage, which is to include the Ctr task to the acquisition process. I am creating the 3 tasks previously with another vi, the vi which creates the counter task (CreateTask6250Ctr.vi) is also attached. Now in the measurement vi (4461-6250ai-6250Ctr.vi), I use the "SampleClock" of the 6250-AI task in order to synchronize the AI with the Ctr task (I am not sure that this is the proper way to do this). Then I ask the "CounterTimebase.Source" in order to know which one is been used as SOURCE signal for the tick counting between the TTL pulses. Finally, I use the same "StartTrigger" signal from the master device to trigger the start of the Ctr task. In this way, when the AI task from the 4461 is started, it give the "StartTrigger" signal to the AI and Ctr tasks from the 6250 and the 3 start at the same time.
What do you think. am I right with my approach?
Is the Ctr task properly created to use the counter as in figure 7-8?
Are the three tasks properly synchronized?
Which other options do I have in order to synchronize the Ctr task with the other 2?
Thanking in advance,
Cristián
Attachments:
4461-6250ai-6250Ctr.vi ‏1561 KB
Fig 7-8 from M SeriesUserManual.jpg ‏16 KB
CreateTask6250Ctr.vi ‏35 KB

Could I also use the PXI_Clk10 as a "ReferenceClock.Source" for the three tasks in order to synchronize them? I mean, instead of using the "SampleClock" of the AI task of the 6250 and the Ctr tasks of the same device. See the attachment to see what I mean.
Greetings,
Cristián
Attachments:
4461-6250ai-6250Ctr - PXI_Clk10.vi ‏1558 KB

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Hi
what if the master instance goes down and comes back? As the slave will be still up and running when the master becomes available will there be any synchronization problems?
Help in finding the solution to this.
Thanks in advance.
Mahesh

No. As soon as your master goes down your slave become master and when old master comes back it join as slave in cluster. See http://crxcluster.wemblog.com/ to understand cluster better.
Yogesh

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Hello All,
Would someone be able to tell me if there are any CLIX commands that allows the slave to synchronize with the master such that only checked in records are transported from master to slave.
Regards
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Hi ,
In free-from search you have option of "expression".
There you can put the option of "Is checkout version".
Hope this helps,
Pls let me know the result.
+ An
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Synchronization - Master and Slave tasks.

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