Trigger two FPGA instances at same time

Question

I have some basic FPGA code that transmits data bits over a serial bus (RS485),  The code is written so that it waits in the first state of a state machine in a single cycle timed loop.  Upon a certain trigger, it starts reading a FIFO containing data and sends the data out on a Tx line.  It does this until all bits are send then it goes back to the first state to wait for the next trigger.  The trigger is needed because windows has to fill the FIFO first before the FPGA can start sending.
I need two instances of this code running because I have two com busses (one is redundant).  So I am using the FPGA code as a subvi and I wrote a main FPGA vi to call two separate instances of the subvi in parallel.  A regular windows vi writes to the FIFOs for Tx and reads FIFOs for Rx.  No problem so far.
The trick is that I have to start both transmissions within 200nS of each other (yes, nanoseconds).  Windows will write to both FIFOs in parallel, but the timing is 4uS apart, too long.  I tried setting up a boolean flag in the FPGA subvi, but windows can't write to the subvi control directly.  FPGA won't allow it (the Write function is greyed out).  I tried using a FIFO for a flag, but the problem is a race condition.  One of the instances will read the FIFO first and wipe it out.  The other does not get to read it.  I need one common trigger point to be used by both subvi instances.
My final solution was to use a memory in the FPGA subvi and a numeric control in the main FPGA vi.  Windows write to the numeric control,  It can because the control is in the main FPGA vi.  Inside the main FPGA, I run a timed loop that looks for the numeric to be other than zero.  If so, it writes the value to the memory location used by the FPGA subvi.  After some time, the main writes a zero back to the memory to prevent the subvi from starting up again, and it writes a zero to the numeric to reset it.  The whole thing repeats, waiting for windows to write to the numeric again for the next transmission.
I had to do it this way because sometimes I want to transmit on both busses, and sometimes just one or the other.  Numeric values are used to determine which to transmit on.  Now the transmissions start at almost exactly the same time, 1 or 2 nanoseconds apart.  But the trigger process seems very far fetched to me.  I was wondering if there is a better solution.  I'm pretty new to FPGA.
- tbob
Inventor of the WORM Global
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Answer 1

tbob wrote:
Basically I did the same thing using FPGA Memory.  From windows I write to a numeric control which resides inside the FPGA Main vi.  In the FGPA main, I write to the Memory.  Inside the FPGA subvi, I read the memory and decode the value to either use one or the other or both busses.  After fooling with this for some time, because the Read Memeory needs to use a shift register (probably due to it taking an entier clock cycle), I got it to work.  Both busses trigger at the same time.  I guess it really doesn't matter if I use a FIFO or if I use Memory.  The main issue is that I have to write from Windows to the FPGA Main, and then from the FPGA Main to the FPGA subvi.  Then the timing is exact as far as the subvi is concerned.
There are a couple of advantages to using two FIFOs over your approach.  First, you don't need the shift register for the memory location.  Second, you don't have to worry about which VI is responsible for clearing the memory location, nor do you run the risk that one of your subVIs will execute twice, or not at all, if the memory isn't cleared at the right time.  Perhaps most importantly, you'll save yourself space on the FPGA because you won't need arbitration - the extra code that gets added when two parts of the FPGA try to access the same resource at the same time.  In your case, both instances of the subVI access the memory block concurrently, so the FPGA compiler adds extra logic to prevent conflicts.  If you only read the memory block in one place and only write it in one place (the read and write can be in different loops or subVIs) there's no need for arbitration.  By using two FIFOs you can keep them independent and avoid the conflict resolution code.  See the help for "arbitration" for more details.