Vivado 2014.4 - What issues the "set_property" command?

Question

I have a design with a custom AXI4 peripheral that is quite large with many IP cores. When I open the peripheral in "IP Packager" and synthesize I see a clue to what may be causing Implementation to fail in the main project due to not finding some IP in the AXI4 peripheral.
Here is a portion of the log file of a synthesis run:
# read_ip i:/axi_bmdl_modem_1.0/src/Rx_SRRC4_FIR_LPF/Rx_SRRC4_FIR_LPF.xci
# set_property is_locked true [get_files i:/axi_bmdl_modem_1.0/src/Rx_SRRC4_FIR_LPF/Rx_SRRC4_FIR_LPF.xci]
# read_ip i:/axi_bmdl_modem_1.0/src/Sync_FIFO_16x12/Sync_FIFO_16x12.xci
# set_property used_in_implementation false [get_files -all i:/axi_bmdl_modem_1.0/src/Sync_FIFO_16x12/Sync_FIFO_16x12/Sync_FIFO_16x12_clocks.xdc]
# set_property used_in_implementation false [get_files -all i:/axi_bmdl_modem_1.0/src/Sync_FIFO_16x12/Sync_FIFO_16x12/Sync_FIFO_16x12.xdc]
# set_property used_in_implementation false [get_files -all i:/axi_bmdl_modem_1.0/src/Sync_FIFO_16x12/Sync_FIFO_16x12_ooc.xdc]
# set_property is_locked true [get_files i:/axi_bmdl_modem_1.0/src/Sync_FIFO_16x12/Sync_FIFO_16x12.xci]
The text in black is a FIR filter that correctly synthesises and runs through implementation OK. Note the it does a "read" and then a "set_property is_locked true"
The text in red is a FIFO that generates a warning in the main project when I synthesize the entire project:
[Designutils 20-1280] Could not find module 'Sync_FIFO_16x12'. The XDC file c:/VHDL_Projects/BMDL_SDR1/BMDL_SDR1.srcs/sources_1/bd/bmdl_sdr_design/ip/bmdl_sdr_design_axi_bmdl_modem_0_0/src/Sync_FIFO_16x12/Sync_FIFO_16x12/Sync_FIFO_16x12.xdc will not be read for any cell of this module.
It also generates an error in Implementation in the main project that says it can't be found. Note the it does a "read" and then a "set_property used_in_implementation false" followed by a "set_property is_locked true"
My question is about the "set_property used_in_implementation false" command. Why is it being issued for the FIFO and not for the FIR filter? Is there a setting somewhere that tells Vivado to set it to "false" for the FIFO? Why is this happening for some of the IP and not others? For the life of me I can't see any differences in properties between the IP that works and the IP that doesn't. Maybe I'm just tired and I'm missing something obvious.
Any ideas??
Thanks,
Kevin

Answer 1

Vinay,
Checking the "Implementation" checkbox didn't help. I believe the Implementation error is the product of a synthesis issue.
So, I have an AXI4 peripheral that contains several IP. I do the following:
In the Block diagram of the main project I right-click on the AXI4 periheral and select "Edit in IP Packager".
I run synthesis in IP Packager. The results look good. I even can open a Schematic and scope around the peripheral design and everything is there.
I re-package and the IP project closes.
Back in the main project I run synthesis.
Synthesis complains about missing items, mostly FIFO IP but also one block of VHDL code instantiated in the design. Scoping around the schematic shows missing items in the design.
This design ran all the way through Implementation a couple of weeks ago. It's like there's some gremlin running around the design that I can't get rid of. 
I decided to go through the log file of the current design and a known good early design. First thing that is different in the log file of the current design is the following critical warning:
CRITICAL WARNING: [Synth 8-2488] overwriting existing primary unit ad16_defs...
Which is refering to a VHDL package used in another AXI4 periheral. The known good project from two weeks ago didn't use that package in the second AXI4 peripheral. I wonder if that could be the problem although the twp package files should be identical? How do I get around that problem?
I'm still going through the two log files looking for differences...
Kevin