WS applicaiton undefined but shows in error

Hi all,
User creates new 2D and 3D drawings using CATIA. Switched to CAD desktop using CDI tool.
Selects 2 files (one is of CATIA and nother is of pdf formats) file and clicks on "check in originals".
As soon as he clicks on check in orginal a pop up error message appears stating WS application TIC not defined.
Now PDF file is checked in but not CATIA file. Now he checks in again selecting only CATIA it doesnt throw any error.
In DC 30 this WS appl TIC is not defined. But when this TIC is not defined and PDF and catia file extensions are already available in another WS applciation why is this error occruing. This is happening while chkcing in files thorugh CAD desk top.
More over when files are getting checked in sepeartealy this error is not popin up its ppearing only first time when both files are selected together.
Any help
Regards,
satish

HI Satish,
Try with latest SAP GUI 730 patch and ECL viewer versions.
Thanks,
Chandu.

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PAR done but shows PAR Error on planahead 14.7

hi,
am getting PAR error while in log it shows PAR done!!!
this happens only when i change the reset pin of my design from V5 to any other pin.
my design consists of microblaze also.
Thanks

following is the logi file
*** Running ngdbuild
with args -intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc "top_module.ucf" -bm "top_module.bmm" "top_module.edf"
Command Line:
D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe
-intstyle ise -p xc6slx45fgg484-2 -dd _ngo -uc top_module.ucf -bm top_module.bmm
top_module.edf
Executing edif2ngd -quiet "top_module.edf" "_ngo\top_module.ngo"
Release 14.7 - edif2ngd P.20131013 (nt64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading NGO file
"D:/BEL_DRC/BEL_DRC/mohammad_ADC_july24/spartan6_adc2.runs/impl_1/_ngo/top_modul
e.ngo" ...
Gathering constraint information from source properties...
Done.
Annotating constraints to design from ucf file "top_module.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
Done...
Processing BMM file "top_module.bmm" ...
Checking expanded design ...
WARNING:NgdBuild:443 - SFF primitive
'test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Perform
ance.Decode_I/Using_FPGA.Gen_Bits[27].MEM_EX_Result_Inst' has unconnected
output pin
Partition Implementation Status
No Partitions were found in this design.
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 1
Writing NGD file "top_module.ngd" ...
Total REAL time to NGDBUILD completion: 37 sec
Total CPU time to NGDBUILD completion: 9 sec
Writing NGDBUILD log file "top_module.bld"...
NGDBUILD done.
*** Running map
with args -intstyle pa -w "top_module.ngd"
Using target part "6slx45fgg484-2".
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
(.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 17 secs
Total CPU time at the beginning of Placer: 16 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:1f7146f2) REAL time: 19 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:1f7146f2) REAL time: 19 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:c84c17d2) REAL time: 19 secs
Phase 4.2 Initial Placement for Architecture Specific Features
Phase 4.2 Initial Placement for Architecture Specific Features
(Checksum:fb9deab) REAL time: 38 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:fb9deab) REAL time: 38 secs
Phase 6.30 Global Clock Region Assignment
Phase 6.30 Global Clock Region Assignment (Checksum:fb9deab) REAL time: 38 secs
Phase 7.3 Local Placement Optimization
Phase 7.3 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:fb9deab) REAL time: 39 secs
Phase 9.8 Global Placement
Phase 9.8 Global Placement (Checksum:fe784d) REAL time: 53 secs
Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:fe784d) REAL time: 53 secs
Phase 11.18 Placement Optimization
Phase 11.18 Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 3 secs
Phase 12.5 Local Placement Optimization
Phase 12.5 Local Placement Optimization (Checksum:bc17e6b8) REAL time: 1 mins 4 secs
Phase 13.34 Placement Validation
Phase 13.34 Placement Validation (Checksum:ee3892b6) REAL time: 1 mins 4 secs
Total REAL time to Placer completion: 1 mins 13 secs
Total CPU time to Placer completion: 1 mins 9 secs
Running post-placement packing...
Writing output files...
Design Summary:
Number of errors: 0
Number of warnings: 19
Slice Logic Utilization:
Number of Slice Registers: 2,768 out of 54,576 5%
Number used as Flip Flops: 2,761
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,495 out of 27,288 9%
Number used as logic: 2,244 out of 27,288 8%
Number using O6 output only: 1,810
Number using O5 output only: 48
Number using O5 and O6: 386
Number used as ROM: 0
Number used as Memory: 157 out of 6,408 2%
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 93
Number using O6 output only: 26
Number using O5 output only: 1
Number using O5 and O6: 66
Number used exclusively as route-thrus: 94
Number with same-slice register load: 90
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,309 out of 6,822 19%
Number of MUXCYs used: 228 out of 13,644 1%
Number of LUT Flip Flop pairs used: 3,563
Number with an unused Flip Flop: 1,031 out of 3,563 28%
Number with an unused LUT: 1,068 out of 3,563 29%
Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
Number of unique control sets: 256
Number of slice register sites lost
to control set restrictions: 1,096 out of 54,576 2%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 316 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 32 out of 116 27%
Number of RAMB8BWERs: 8 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 14 out of 16 87%
Number used as BUFGs: 14
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 5 out of 8 62%
Number used as DCMs: 5
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.63
Peak Memory Usage: 536 MB
Total REAL time to MAP completion: 1 mins 18 secs
Total CPU time to MAP completion: 1 mins 14 secs
Mapping completed.
See MAP report file "top_module.mrp" for details.
*** Running par
with args -intstyle pa "top_module.ncd" -w "top_module_routed.ncd"
Constraints file: top_module.pcf.
Loading device for application Rf_Device from file '6slx45.nph' in environment
D:\InstalledSW\Xilinx147\14.7\ISE_DS\ISE\.
"top_module" is an NCD, version 3.2, device xc6slx45, package fgg484, speed -2
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
Device speed data version: "PRODUCTION 1.23 2013-10-13".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 2,768 out of 54,576 5%
Number used as Flip Flops: 2,761
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 7
Number of Slice LUTs: 2,495 out of 27,288 9%
Number used as logic: 2,244 out of 27,288 8%
Number using O6 output only: 1,810
Number using O5 output only: 48
Number using O5 and O6: 386
Number used as ROM: 0
Number used as Memory: 157 out of 6,408 2%
Number used as Dual Port RAM: 64
Number using O6 output only: 0
Number using O5 output only: 0
Number using O5 and O6: 64
Number used as Single Port RAM: 0
Number used as Shift Register: 93
Number using O6 output only: 26
Number using O5 output only: 1
Number using O5 and O6: 66
Number used exclusively as route-thrus: 94
Number with same-slice register load: 90
Number with same-slice carry load: 4
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 1,309 out of 6,822 19%
Number of MUXCYs used: 228 out of 13,644 1%
Number of LUT Flip Flop pairs used: 3,563
Number with an unused Flip Flop: 1,031 out of 3,563 28%
Number with an unused LUT: 1,068 out of 3,563 29%
Number of fully used LUT-FF pairs: 1,464 out of 3,563 41%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
clock, reset, set, and enable signals for a registered element.
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
IO Utilization:
Number of bonded IOBs: 4 out of 316 1%
Number of LOCed IOBs: 4 out of 4 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 32 out of 116 27%
Number of RAMB8BWERs: 8 out of 232 3%
Number of BUFIO2/BUFIO2_2CLKs: 1 out of 32 3%
Number used as BUFIO2s: 1
Number used as BUFIO2_2CLKs: 0
Number of BUFIO2FB/BUFIO2FB_2CLKs: 1 out of 32 3%
Number used as BUFIO2FBs: 1
Number used as BUFIO2FB_2CLKs: 0
Number of BUFG/BUFGMUXs: 14 out of 16 87%
Number used as BUFGs: 14
Number used as BUFGMUX: 0
Number of DCM/DCM_CLKGENs: 5 out of 8 62%
Number used as DCMs: 5
Number used as DCM_CLKGENs: 0
Number of ILOGIC2/ISERDES2s: 0 out of 376 0%
Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 376 0%
Number of OLOGIC2/OSERDES2s: 0 out of 376 0%
Number of BSCANs: 1 out of 4 25%
Number of BUFHs: 0 out of 256 0%
Number of BUFPLLs: 0 out of 8 0%
Number of BUFPLL_MCBs: 0 out of 4 0%
Number of DSP48A1s: 3 out of 58 5%
Number of ICAPs: 0 out of 1 0%
Number of MCBs: 0 out of 2 0%
Number of PCILOGICSEs: 0 out of 2 0%
Number of PLL_ADVs: 1 out of 4 25%
Number of PMVs: 0 out of 1 0%
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Overall effort level (-ol): Standard
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 8 secs
Finished initial Timing Analysis. REAL time: 8 secs
WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[31] has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[12].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[9].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[13].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[7].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[4].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal test_module_inst/mb_inst/dlmb_LMB_ABus[30] has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[11].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[8].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[6].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[5].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[1].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[0].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[14].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[10].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[15].ra
m32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[2].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
WARNING:Par:288 - The signal
test_module_inst/mb_inst/microblaze_0/microblaze_0/MicroBlaze_Core_I/Performance.Data_Flow_I/Register_File_I/Using_LUT6.All_RAM32M[3].ram
32m_i_RAMD_D1_O has no load. PAR will not attempt to route this signal.
Starting Router
Phase 1 : 20567 unrouted; REAL time: 9 secs
Phase 2 : 15210 unrouted; REAL time: 13 secs
WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish the rest of the
design and leave them as unrouted. The cause of this behavior is either an issue with the placement or unroutable placement constraints.
To allow you to use FPGA editor to isolate the problems, the following is a list of (up to 10) such unroutable connections:
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[0].clk_wizard_inst/dcm_sp_inst/CLKIN
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[2].clk_wizard_inst/dcm_sp_inst/CLKIN
Unroutable signal: clk_adc_sig pin: test_module_inst/adc_wrapper_inst/clk_wizard_gen[3].clk_wizard_inst/dcm_sp_inst/CLKIN
Phase 3 : 5729 unrouted; REAL time: 33 secs
Phase 4 : 5729 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 35 secs
Updating file: top_module_routed.ncd with current fully routed design.
Phase 5 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 6 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 7 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 8 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 9 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 49 secs
Phase 10 : 3 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 50 secs
Total REAL time to Router completion: 50 secs
Total CPU time to Router completion: 50 secs
Partition Implementation Status
No Partitions were found in this design.
Generating "PAR" statistics.
Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
| inst/clk_50_0000MHz | BUFGMUX_X2Y10| No | 960 | 0.064 | 1.774 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[0] | BUFGMUX_X2Y9| No | 28 | 0.057 | 1.766 |
+---------------------+--------------+------+------+------------+-------------+
| clk_rd_sig | BUFGMUX_X2Y4| No | 104 | 0.052 | 1.770 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[1] | BUFGMUX_X2Y11| No | 28 | 0.028 | 1.743 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[2] | BUFGMUX_X2Y1| No | 27 | 0.031 | 1.771 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk180 | | | | | |
| _sig[3] | BUFGMUX_X3Y8| No | 27 | 0.028 | 1.739 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
|inst/microblaze_0_md | | | | | |
| m_bus_Dbg_Clk | BUFGMUX_X3Y13| No | 61 | 0.055 | 1.767 |
+---------------------+--------------+------+------+------------+-------------+
| clk_counter_sig | BUFGMUX_X2Y2| No | 2 | 0.002 | 1.738 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[1] | BUFGMUX_X3Y5| No | 2 | 0.000 | 1.770 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[0] | BUFGMUX_X3Y15| No | 7 | 0.045 | 1.767 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[3] | BUFGMUX_X3Y16| No | 2 | 0.000 | 1.722 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clkout | | | | | |
| _wiz_sig[2] | BUFGMUX_X2Y12| No | 2 | 0.000 | 1.766 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/adc | | | | | |
|_wrapper_inst/clk270 | | | | | |
| _sig[0] | BUFGMUX_X3Y14| No | 4 | 0.022 | 1.765 |
+---------------------+--------------+------+------+------------+-------------+
|test_module_inst/mb_ | | | | | |
|inst/microblaze_0_md | | | | | |
| m_bus_Dbg_Update | Local| | 20 | 4.177 | 6.233 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.
Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)
Number of Timing Constraints that were not applied: 1
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
TS_test_module_inst_mb_inst_clock_generat | SETUP | 7.791ns| 12.209ns| 0| 0
or_0_clock_generator_0_SIG_PLL0_CLKOUT0 | HOLD | 0.240ns| | 0| 0
= PERIOD TIMEGRP "test_mod | | | | |
ule_inst_mb_inst_clock_generator_0_clock_ | | | | |
generator_0_SIG_PLL0_CLKOUT0" TS_ | | | | |
sys_clk_pin HIGH 50% | | | | |
TS_sys_clk_pin = PERIOD TIMEGRP "sys_clk_ | MINLOWPULSE | 15.000ns| 5.000ns| 0| 0
pin" 50 MHz HIGH 50% | | | | |
Derived Constraint Report
Review Timing Report for more details on the following derived constraints.
To create a Timing Report, run "trce -v 12 -fastpaths -o design_timing_report design.ncd design.pcf"
or "Run Timing Analysis" from Timing Analyzer (timingan).
Derived Constraints for TS_sys_clk_pin
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
| | Period | Actual Period | Timing Errors | Paths Analyzed |
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_sys_clk_pin | 20.000ns| 5.000ns| 12.209ns| 0| 0| 0| 358509|
| TS_test_module_inst_mb_inst_cl| 20.000ns| 12.209ns| N/A| 0| 0| 358509| 0|
| ock_generator_0_clock_generato| | | | | | | |
| r_0_SIG_PLL0_CLKOUT0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
All constraints were met.
Generating Pad Report.
1 signals are not completely routed. See the top_module_routed.unroutes file for a list of all unrouted signals.
WARNING:Par:100 - Design is not completely routed. There are 1 signals that are not
completely routed in this design. See the "top_module_routed.unroutes" file for a list of
all unrouted signals. Check for other warnings in your PAR report that might
indicate why these nets are unroutable. These nets can also be evaluated
in FPGA Editor by selecting "Unrouted Nets" in the List Window.
WARNING:Par:283 - There are 18 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 53 secs
Total CPU time to PAR completion: 52 secs
Peak Memory Usage: 515 MB
Placer: Placement generated during map.
Routing: Completed - errors found.
Timing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 23
Number of info messages: 0
Writing design to file top_module_routed.ncd
PAR done!

Java Mail Madness - Doesn't Work but shows no errors ?

What's up folks. I am trying to implement the java mail library. Unfortunately, I have a problem and I don't know how to track it down. Here is the code that I run in the Netbeans IDE.
import java.io.*;
import javax.mail.*;
import javax.mail.internet.*;
import javax.activation.*;
public class SendApp {
public static void send(String smtpHost, int smtpPort,
String from, String to,
String subject, String content)
throws AddressException, MessagingException {
// Create a mail session
java.util.Properties props = new java.util.Properties();
props.put("mail.smtp.host", smtpHost);
props.put("mail.smtp.port", ""+smtpPort);
Session session = Session.getDefaultInstance(props, null);
// Construct the message
Message msg = new MimeMessage(session);
msg.setFrom(new InternetAddress(from));
msg.setRecipient(Message.RecipientType.TO, new InternetAddress(to));
msg.setSubject(subject);
msg.setText(content);
// Send the message
Transport.send(msg);
public static void main(String[] args) throws Exception {
// Send a test message
send("kernel", 25, "jd@kernel", "[email protected]",
"re: dinner", "How about at 7?");
Where kernel is the domain name of my computer. However, when I check my email at [email protected] (fake address) I don't see anything and the program exits with success. I don't know if this is cause of a problem with my Netbeans, my code, or my postfix smtp system. Any help is greatly appreciated !
SIncerely,
Justin Dallas

Hi,
Did you checked the log for any errors
catch (Exception e) {
System.out.println("Exception while sending mail" + e.getMessage());
e.printStackTrace();
Or else add the following line in your exception handler and check whether their is any error or not.
wdComponentAPI.getMessageManager().reportException(e.getMessage());
Regards
Ayyapparaj

Not overriding the coherence-cache-config.xml but showing the error...

Hi,
I have created a file called tangosol-coherence-override.xml file in the specified path which is " C:\Program Files\Oracle\Coherence for .NET"
and the coherence.jar file is located in path which is "C:\Program Files\Oracle\Coherence for .NET\lib"
but it is not overriding the xml file.. with the default file...
C:\Program Files\Oracle\Coherence for .NET\examples\ContactCache.Java>"C:\Progra
m Files\Java\jdk1.6.0_11\bin\java" -server -showversion -Xms128m -Xmx128m -Dtang
osol.coherence.ttl=0 -Dtangosol.coherence.cacheconfig=contact-cache-config.xml -
cp "config;lib\custom-types.jar;C:\Program Files\Oracle\Coherence for .NET\lib\c
oherence.jar" com.tangosol.net.DefaultCacheServer
java version "1.6.0_11"
Java(TM) SE Runtime Environment (build 1.6.0_11-b03)
Java HotSpot(TM) Server VM (build 11.0-b16, mixed mode)
2011-06-20 15:06:57.607/2.366 Oracle Coherence 3.7.0.0 <Info> (thread=main, memb
er=n/a): Loaded operational configuration from "jar:file:/C:/Program%20Files/Ora
cle/Coherence%20for%20.NET/lib/coherence.jar!/tangosol-coherence.xml"
2011-06-20 15:06:57.989/2.748 Oracle Coherence 3.7.0.0 <Info> (thread=main, memb
er=n/a): Loaded operational overrides from "jar:file:/C:/Program%20Files/Oracle/
Coherence%20for%20.NET/lib/coherence.jar!/tangosol-coherence-override-dev.xml"
2011-06-20 15:06:58.049/2.808 Oracle Coherence 3.7.0.0 <D5> (thread=main, member
=n/a): Optional configuration override "/tangosol-coherence-override.xml" is not
specified
2011-06-20 15:06:58.062/2.821 Oracle Coherence 3.7.0.0 <D5> (thread=main, member
=n/a): Optional configuration override "/custom-mbeans.xml" is not specified
Oracle Coherence Version 3.7.0.0 Build 23397
Grid Edition: Development mode
Thanks in Advance

The CLASSPATH is not the same as the PATH. It is similar but a classpath is a set of directories or jar files that Java uses to look for executable code and resources.
Assuming you are using the example start-cache-server.cmd file that comes with the .Net examples to start your server you can put the tangosol-coherence-override.xml file into the C:\Program Files\Oracle\Coherence for .NET\examples\ContactCache.Java\config directory as this is on the classpath when using that script.
JK

Interface execution done(but showing some error in Operator on seeing execution)

Hi Folks,
There is the following error coming while execution of interface.
ODI-1217: Session INT_INFext_RT_FF (20001) fails with return code 30088.
ODI-1226: Step INT_INFext_RT_FF fails after 1 attempt(s).
ODI-1240: Flow INT_INFext_RT_FF fails while performing a Loading operation. This flow loads target table TRG_SALES_PERSON.
ODI-1228: Task SrcSet0 (Loading) fails on the target ORACLE connection ODI_STAGE.
Caused By: java.sql.SQLException: ORA-30088: datetime/interval precision is out of range
at oracle.jdbc.driver.T4CTTIoer.processError(T4CTTIoer.java:462)
at oracle.jdbc.driver.T4CTTIoer.processError(T4CTTIoer.java:405)
Regards
Rachin Gupta

Sorry for the delay. See document 741294.1 in support system. Based on the document this is generally caused by Incorrect mapping between columns or Incorrect datatype conversion specification. To resolve:
Verify the Column attributes of target table
Verify the Column Converted to tab
Verify the Converted from tab
Jani Rautiainen
Fusion Applications Developer Relations
https://blogs.oracle.com/fadevrel/

HT204053 Dear Support Team, every time i tried to logon Icloud its gives me wrong user name or password and at the end it show me error " This Apple ID is valid but is not an ICloud Account" then how can i use one account for same Apple ID and ICloud???

Dear Support Team,
Every time i tried to logon Icloud its gives me wrong user name or password and at the end it show me error " This Apple ID is valid but is not an ICloud Account" then how can i use one account for same Apple ID and ICloud?
Thanks

It is not possible to create a new iCloud account using a Windows machine. You must create the account using a Mac (10.7.5 or more) or an IOS device (iPhone etc). Once that is done you can sign into and use the account on your Windows machine.

HT201210 Whenever I update my iPhone when update is available, after completing every process it shows an error that iPhone could not be updated and my iPhone goes into recovery mode but when I recover it it still doesn't work and shows the same error. H

I tried to update my iPhone running 6.1.2 to 6.1.3 it showed an error and went into recovery mode but when I try to restore it it doesnt even got restored.......... ! Please Help !!!

See Here > http://support.apple.com/kb/HT1808
You may need to try this More than Once...
Be sure to Follow ALL the Steps...
But... if the Device has been Modified... this will Not necessarily work.

I have disabled pop ups in my iphone but still i could n't connect to my college wifi.. It shows the error message as ensure whether the pop ups are not blocked.. pls help

Hai..
I have disabled block pop up in my iphone 5s.. but still i couldn't connect my mobile with my college wifi.. it shows the error message as "ensure all the pop ups are not blocked"....

You might want to talk to the IT dept. at your school to see if they know of a solution.

Hi i got a brand new ipod touch 4g a week back.as my friend said i jailbroke it with redsnow.but now i try to restore itunes is showing unknown error(3194).what to do?

i jailbroke my new ipod touch 4g with redsnow and as i have no wi-fi i installed appsync and installous by placing .DEB files of the same in cydia via i-funbox on my pc and rebooted ipod.then i was able to intall any app.but i found jailbreaking is not good and voids warranty i tried to restore it.i-tunes downloaded the ios and then i tried to restore ipod i-tunes says 'unknown error(3194)'.i have latest version of i-tunes installed(10.5.3).i also have a broad band connection.
i once tried to get SHSH blobs from tinyumbrella and i-faith but did not succeded.
now ipod is very slow,stucks and also i-books is not supporting(shows configuration error.restore ur ipod).
so for all these reasons i want to restore my ipod.so please help me.thank you guys.

That is not true. Jaibreaking is not illegal and Apple can't seize your device if yu do. The can just refuse service like help in this Apple forum.
See:
Jailbreaking iPhone Is Legal, U.S. Government Says - ABC News

TS2446 my app store is not working, i tired signing in but showing me "An unknown error has occurred" my password is not wrong, please and someone help, because i need to update my macbook air. thank you

my app store is not working, i tired signing in but showing me "An unknown error has occurred" my password is not wrong, please and someone help, because i need to update my macbook air. thank you... how can i make it work?

I cannot sign out. When I go to the iTunes & App Stores in settings, The Apple ID field shows my id but it is faded and I cannot select the field.

I am unable to install photoshop elements13 due to an error. it shows no error code but does say - This installer does not support installation on a 64-Bit Windows operating system. Please download the 64-Bit version of Photoshop Elements.

i am unable to install photoshop elements13 due to an error. it shows no error code but does say - This installer does not support installation on a 64-Bit Windows operating system. Please download the 64-Bit version of Photoshop Elements.

download the 64bit installer,
Downloads available:
Suites and Programs: CC 2014 | CC | CS6 | CS5.5 | CS5 | CS4 | CS3
Acrobat: XI, X | 9,8 | 9 standard
Premiere Elements: 13 | 12 | 11, 10 | 9, 8, 7 win | 8 mac | 7 mac
Photoshop Elements: 13 |12 | 11, 10 | 9,8,7 win | 8 mac | 7 mac
Lightroom: 5.7| 5 | 4 | 3
Captivate: 8 | 7 | 6 | 5
Contribute: CS5 | CS4, CS3
Download and installation help for Adobe links
Download and installation help for Prodesigntools links are listed on most linked pages. They are critical; especially steps 1, 2 and 3. If you click a link that does not have those steps listed, open a second window using the Lightroom 3 link to see those 'Important Instructions'.

HT4623 I am having 4S. It is showing the IOS 6 update, but whenever I try to update it, it shows an error message saying " It cannot be downloaded at this time". Can someone please tell me how to update it?

I am having 4S. It is showing the IOS 6 update, but whenever I try to update it, it shows an error message saying " It cannot be downloaded at this time". Can someone please tell me how to update it?

Make sure you have the Latest version of iTunes on your computer.
Connect to iTunes on the computer you usually Sync with and “ Check for Updates “...
See the Using iTunes Section Here...
How to update your iPhone, iPad, or iPod touch

ITunes keep showing unknown error 48 while restoring iphone 4s. I've already followed applesupport suggestions of reinstalling iTunes, deleting previously downloaded ipsw on my computer and re-downloading it (countless times!) but still to no avail.

Hi. A very much help needed.
- iTunes keep showing unknown error (48) while restoring my iphone 4s
- I've already re-install iTunes various times
- Already delete previously downloaded 8.3 ipsw and re-downloaded it countless times
- Changed and edited hosts in windows drivers as per shown on guides
but... to no avail!!!!
I am now without any phone to be used.
HELP ME PLEASE

Hello Sean,
It sounds like you are constantly needing to restore your phone because it keeps going into recovery mode. Usually putting a device into recovery mode and restoring it can help isolate an issue to your iPhone hardware if an issue persists afterwards. I would try manually putting it into recovery mode and restoring it 1 more time:
If you can't update or restore your iOS device
http://support.apple.com/kb/HT1808
If that does not resolve it the symptoms indicate to me that it is a hardware issue causing this to happen and would seek service for it:
iPhone Repair - Other Repairs
https://www.apple.com/support/iphone/repair/other/
Thank you for using Apple Support Communities.
All the best,
Sterling

HT4436 i try to log in using apple id in icloud but it shows me error

i try to log in using apple id in icloud but it shows me error that "apple id must be used to set up icloud in an iSO or OS X Devise before you can use" suggest me what to do if possible
<Email Edited By Host>

The account must be setup using a Mac or an iPhone/iPad. You can not set it up using a PC.

WS applicaiton undefined but shows in error

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