X-series DMA -- single chunky link for finite SGL -- possible?

ok, i guess i stumped you guys on the previous question regarding aout fifo width. here is another one.
can i have a ChInCh SGL program that has a single chunky link, with the done flag set?
i compose the SGL myself (not using the DDK chunky link classes). I have LinkChainRing and ReuseLinkRing SGL working fine. However, if I want to run a finite SGL with one chunky link, I hang in tCHInChDMAChannelController::start waiting for the link ready bit.
so there appears to be an issue with starting a finite DMA SGL on a chunky link that has the Done bit set -- is that right? Is there a way around this?
thanks,
--spg
scott gillespie
applied brain, inc.
Solved!
Go to Solution.

Steven T --
Ok, thanks for verifying that.
>> Is there a reason why you must use one page descriptor in the chunky link?
Not necessarily, however since I am constructing my own SGL's, I do need to know exactly what I can and can't do. So when I see behavior like this, I first want to understand if I am doing something wrong, then determine a workaround if it is a hardware limitation.
As I am writing a driver that supports several different clients, I need to provide a generalized interface that can handle any request. For example, I need to know that if one of my clients requests a single byte transfer, the driver has to fail gracefully (or implement the request without using DMA), and not hang :-)
Having you verify this limitation (if it is that) is extremely useful to me, since I can now deploy the workaround (add an extra transfer for any single link chunky, use a direct write or FIFO preload for any single byte transfer) and not continue to wonder if I have missed some other essential register setting or flag.
Thanks again, and if you do find out anything more, let me know.
cheers,
spg
scott gillespie
applied brain, inc.

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Solved!
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steven t --
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Testing: Speedy X-series 6363 Slot-4
Bar0/Bar1/iBus: 0x1b1000/0x0/0x21df50
X-Series Info -- nameCIe-6363, id=29749, adc:1 ai:32 dac:4
Memrequest: 0000000001000000
Starting finite 100.00-second hardware-timed analog measurement.
Reading 500000-sample chunks from the 500000-sample DMA buffer.
Status_1: 237910b0, StreamControlStatusReg: 00000101
Status_1: 237900b2, StreamControlStatusReg: 00000101
Status_1: 337900b2, StreamControlStatusReg: 00000101
Status_1: 237900b2, StreamControlStatusReg: 00040101
Status_1: 619010f0, StreamControlStatusReg: 00040101
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Read 500000 samples (without overwriting data) using a 500000-sample DMA buffer.
--------- speedy -- Unload Library
-- program loops waiting for data (0 bytes reported available)
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Status_1: 237900b2, StreamControlStatusReg: 00000101
Status_1: 337900b2, StreamControlStatusReg: 00000101
Status_1: 237900b2, StreamControlStatusReg: 00000101
Status_1: 337900b2, StreamControlStatusReg: 00000101
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