Test of design on Zedboard

Question

HI , 
I want to test a designed filter on my zedboard . so kann i do that with vivado or  which programm should i use to test the design  on board and show the result of the filtering with it .  it 's so helpful , if someone send me a tutorial or tell me how i do that ?
thanks 
this is the vhdl code of my filter : 
-- Company:
-- Engineer:
-- Create Date: 01.07.2015 17:36:00
-- Design Name:
-- Module Name: FIR-filter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_signed.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity FIRfilter is
Port ( clk : in STD_LOGIC;
x : in signed (13 downto 0);
y : out signed (13 downto 0));
end FIRfilter;
architecture a of FIRfilter is
signal a,b,c :signed(13 downto 0);
signal k1:signed(2 downto 0):="110";
signal k2:signed(2 downto 0):="010";
begin
process(x,clk)
variable d:signed(16 downto 0 );
begin
if (clk='1') and (clk'event)
then
c<=b;
b<=a;
a<=x;
d:=(k1*a + k2*c);
y<=d(15 downto 2 );
end if ;
end process ;
end a;

Answer 1

check this document
http://impulseaccelerated.com/uploads/3/3/7/7/3377898/microblazetutorials.pdf