About ISIM simulator and Test Bench with verilog, output .txt to Matlab

Question

 
Software  :  ISE 14.3
Simulator : ISim by xilinx.
I am a beginner to learn the verilog and FPGA.
I want to use FPGA to process image. After processing, I require to read the processed data into  Matlab  for matching the results .  
I have  stored  256*256,8bit image into the ROM. 
This is my module.
module image_top
input clka,
input ena,
input rst_n,
output [7:0] douta,
output reg rd_stop
reg[15:0]addra;
always@(posedge clka or negedge rst_n)
begin
if(!rst_n)
addra <= 0;
else if(ena)
addra <= addra + 1;
else
addra <= addra;
end
wire rd_stop_flag;
assign rd_stop_flag = (addra == 65535-1)?1:0;
//reg rd_stop;
always@(posedge clka or negedge rst_n)
begin
if(!rst_n)
rd_stop <= 0;
else if(rd_stop_flag)
rd_stop <= 1;
else
rd_stop <= rd_stop;
end
ImageMem u_imgemem
.clka (clka), // input clka
.ena (ena&&!rd_stop), // input ena
.addra (addra), // input [15 : 0] addra
.douta (douta) // output [7 : 0] douta
endmodule
This is my  TestBench. I am not sure this is correct.
`timescale 1ns / 1ps
// Company:
// Engineer:
module TB_top;
// Inputs
reg clka;
reg ena;
reg rst_n;
// Outputs
wire [7:0] douta;
wire rd_stop;
// Instantiate the Unit Under Test (UUT)
image_top uut
.clka(clka),
.ena(ena),
.rst_n(rst_n),
.douta(douta),
.rd_stop(rd_stop)
integer fp_w,j;
initial
begin
// Initialize Inputs
clka = 0;
ena = 0;
rst_n = 0;
fp_w = $fopen("image_out.txt","w");
// Wait 100 ns for global reset to finish
#100 rst_n =1;
#20 ena = 1;
// Add stimulus here
for(j = 0; j < 65536; j= j+1)
begin
$fwrite(fp_w,"%d\n",douta);
end
$fclose(fp_w);
end
always #5 clka = ~clka;
endmodule
This is my TestBench.
After synthesis, In the  project,there is a' image_out.txt' file,but the datas in it  are  all  zero.
I wonder what is the problem?
This is my simulation waveform by ISIM.
I wonder if ISIM isn't  good to support ''for-loop" or system command like $fwrite?
If true, I have to install the modelsim  simulator.
Thank you for your  reply!
 

Answer 1

The bug is in your testbench.
Inside the for loop, you haven't given any opportunity for time to advance. So, the entire 64K iterations of the loop happen "instantaneously" at the same moment in time. This means that there have been no clock periods inside the loop - you are effectively writing the same output of your design (which is 0) 64K times. Advancing time is necessary since your address counter only changes state once per clock period; so all the fwrite's of dout are getting the data from the same address location.
At very least you need to put an "@(posedge clk)" or at least a #10 inside your for loop to allow time to progress (so that you get the output of the module on different clock periods).
Avrum