Simulation and Testing my results

The attached file is supposed to receive 3 signals from the microcontroller via serial communication in the format
sig1sig2sig3
Is there a way I could simulate and test the file without connecting it to the hardware???
Attachments:
UpdatedDisplay.vi ‏83 KB

Hey Lynn
Thanks for your response.
I did understand what you are trying to say but that only enables me to do the test once
If you notice my file, I have to read the following format in a while loop
sig1sig2sig3
I am trying to find a way whereby i can simulate multiple reads.
Also, I want to channel all the incoming data via "serial read" so as to demonstrate the whole file working as a whole entity (for my presentation)
I am quite aware that there is a "random number generator" and "read from spreadsheet" that could help me accomplish this.
But i just cant figure out the whole logic.

Similar Messages

About ISIM simulator and Test Bench with verilog, output .txt to Matlab

Software : ISE 14.3
Simulator : ISim by xilinx.
I am a beginner to learn the verilog and FPGA.
I want to use FPGA to process image. After processing, I require to read the processed data into Matlab for matching the results .
I have stored 256*256,8bit image into the ROM.
This is my module.
module image_top
input clka,
input ena,
input rst_n,
output [7:0] douta,
output reg rd_stop
reg[15:0]addra;
always@(posedge clka or negedge rst_n)
begin
if(!rst_n)
addra <= 0;
else if(ena)
addra <= addra + 1;
else
addra <= addra;
end
wire rd_stop_flag;
assign rd_stop_flag = (addra == 65535-1)?1:0;
//reg rd_stop;
always@(posedge clka or negedge rst_n)
begin
if(!rst_n)
rd_stop <= 0;
else if(rd_stop_flag)
rd_stop <= 1;
else
rd_stop <= rd_stop;
end
ImageMem u_imgemem
.clka (clka), // input clka
.ena (ena&&!rd_stop), // input ena
.addra (addra), // input [15 : 0] addra
.douta (douta) // output [7 : 0] douta
endmodule
This is my TestBench. I am not sure this is correct.
`timescale 1ns / 1ps
// Company:
// Engineer:
module TB_top;
// Inputs
reg clka;
reg ena;
reg rst_n;
// Outputs
wire [7:0] douta;
wire rd_stop;
// Instantiate the Unit Under Test (UUT)
image_top uut
.clka(clka),
.ena(ena),
.rst_n(rst_n),
.douta(douta),
.rd_stop(rd_stop)
integer fp_w,j;
initial
begin
// Initialize Inputs
clka = 0;
ena = 0;
rst_n = 0;
fp_w = $fopen("image_out.txt","w");
// Wait 100 ns for global reset to finish
#100 rst_n =1;
#20 ena = 1;
// Add stimulus here
for(j = 0; j < 65536; j= j+1)
begin
$fwrite(fp_w,"%d\n",douta);
end
$fclose(fp_w);
end
always #5 clka = ~clka;
endmodule
This is my TestBench.
After synthesis, In the project,there is a' image_out.txt' file,but the datas in it are all zero.
I wonder what is the problem?
This is my simulation waveform by ISIM.
I wonder if ISIM isn't good to support ''for-loop" or system command like $fwrite?
If true, I have to install the modelsim simulator.
Thank you for your reply!

The bug is in your testbench.
Inside the for loop, you haven't given any opportunity for time to advance. So, the entire 64K iterations of the loop happen "instantaneously" at the same moment in time. This means that there have been no clock periods inside the loop - you are effectively writing the same output of your design (which is 0) 64K times. Advancing time is necessary since your address counter only changes state once per clock period; so all the fwrite's of dout are getting the data from the same address location.
At very least you need to put an "@(posedge clk)" or at least a #10 inside your for loop to allow time to progress (so that you get the output of the module on different clock periods).
Avrum

Simulation and Burn producing wildly different results

To try and make a long story short, I have constructed a very, very linear DVD (it's actually going to be turned into a VHS, which if you're wondering why, it's b/c of all things this is the cheapest and most efficient way for us to do Closed Captioning on a VHS program). There are a series of scenarios, each with 3 associated ending videos. For each of these videos, I have a menu declaring the upcoming video.
For ease, let's just call it 1A, 1B, 1C, and so on. When I simulate the program, everything works just fine. It goes through on a linear progression.
However, when I burn and test the program, the menus are all over the place. The videos are in the proper order, but video 2A is proceeded by menu 1B and video 2B is proceeded by 2A, etc., etc. There are about a dozen glitches like this on the disc.
Again, I'm fairly confident the project is set up correctly and a simulation of the project shows that. Is this just some crazy file corruption? Has anyone run into such a thing? It's quite disconcerting.
Message was edited by: rw-media12

So I burnt it on a different system and had NO problems. Go figure. It must be some kind of corruption on my other system.

Ipad and Iphone WIFI speed tested weird results

Hi:
Just to help (or make it worse).
I am sitting at my desk and testing my IPad and my Iphone.
I am running the speedtest app from the app store.
The Iphone consistenly gets 14+mbit download (I have a 50mbit ISP link) and just under 5mbit Upload (I have a 5mbit upload link).
The IPAD gets at BEST 7.8mbit down, but also gets just under 5mbit up. So it's even weirder than it seems. The IPAD gets the same upload speed and 1/2 the download speed.
I am testing them on the same network, same location, same everything (wireless G only setting on Router). I am testing them one after the other not simultaneously.
Oh and I couldn't get the IPAD to connect to Wirless N AT ALL.

I guess you both are new here.
Lots of iPad users are plagued by terrible slow wifi connections. There was a thread here "weak wifi" with over 80,000 views and 37 pages of replies.
I too had the same issue then I changed my N capable router to G only mode and my speed Is amazing. Well this is not a solution but hopefully temporary work around until apple comes out with a firmware update.
Write to apple in their iPad feedback form so that they listen to it.they don't look at the forums supposedly.
http://www.apple.com/feedback/ipad.html
Bottom line here is you guys are not alone.
Regrads,

Vivado 2015.2: Simulation and synthesis reverse bit order of std_logic_vector in logical operators

In both simulation and synthesis the logical operators on std_logic_vector bit-reverse the operands in the result, at least in the case where the result of the expression is passed to a function.
I suspect this issue applies to other operators as well, though I have only tested the problem with the logical operators. I also suspect the issue exists in other situations where a function is not involved.
This is incompatible with both ModelSim simulation and XST synthesis and it breaks a lot of our code.
The attached xsim7.vhd example shows the issue. The xsim7.tcl script will run the Vivado simulation. Under Windows, the xsim7.bat will run the whole thing. The xsim7.xpr project file allows synthesis under Vivado, and you can look at the schematic to see the issue in the synthesized netlist.
The source module also simulates under ModelSim and synthesizes under XST, and these show what I believe to be correct behavior.
Can someone please verify this error and either file a CR or tell me to file an SR?
Ian Lewis
www.mstarlabs.com

Hello Bharath,
When I said "what was index 'LOW becomes index 'HIGH" I meant the 'LOW of the source operands and the 'HIGH of the result, independent of the actual index range. I would have no problem with any 'HIGH and 'LOW on the result of the operator as long as the direction matched the left source operand, though personally I would prefer the same 'HIGH and 'LOW as that of the left operand.
Looking at the IEEE implementation of logical "or" on std_logic_vector from package std_logic_1164: https://standards.ieee.org/downloads/1076/1076.2-1996/std_logic_1164-body.vhdl:
-- or
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
the operator does exactly what Vivado seems to be doing: alias the downto source vectors to a to range of 1 to 'LENGTH and then return a vector of 1 to 'LENGTH. This both bit reverses the downto indexes (the alias on the source operands does that) and changes the range to "to" with a 'LOW value of 1.
This gives us the 'LEFT 1 and 'RIGHT 4 we see.
So far, I have found no definition from IEEE of what logical operators, such as "or", are supposed to do on std_logic_vector except as defined by this piece of code for "or" and the other operators' associated bodies from the std_logic_1164 package.
What this code does seems like a horrible decision about how to implement the logical operators on std_logic_vector with respect to range direction, but it is compatible with what Vivado does, and incompatible with what XST does. (I had never investigated this issue before because what ModelSim and XST did made perfect sense to me.)
That the assignment (Result := s) works as expected, makes sense. The assignment of the "to" range s to the "downto" range Result maintains the 'LEFT relationship. That is, Result'LEFT (index 3) receives s'LEFT (index 1). So, the bits are reversed a second time.
That ISIM does not match what XST does seems like a defect no matter how you look at it. Your simulation can never match your synthesis if you care about the range direction inside a function (and I suspect in other places too). This deserves an SR or CR if you are still doing any work on those two tools. I think you may not be.
Are you able to find out whether Vivado was changed from XST on purpose with respect to the behavior of logical operators?
If this is "as designed" then I have to start working on updating our code to live with it. But, if this is something that happened by accident, and you will change Vivado to match XST, then I probably want to wait. Updating our code to live with this behavior is going to be a pretty big job.
Thank you for your help,
Ian

Simulation and design

Plz, can any one tell me
If there is any program that I can desgin a network with Routers and switches, and make simulation on it to test and see the result
and thanks

Assalam-O-Alikum Anas,
Here is the link to the very best simulation program which is free....
http://www.gns3.net/
download and run this application. But you will need Cisco IOS for each platform. If you have CCO account with H/W and Software maintenance, then download and copy into relevant directory.
There are loads of technotes and video tutorials you can access from the same site as well as loads of tutorials on Youtube.com
Hope this helps....
Shaheen

How do I create a 1d array that takes a single calculation and insert the result into the first row and then the next calculation the next time the loop passes that point and puts the results in thsecond row and so on until the loop is exited.

The attached file is work inprogress, with some dummy data sp that I can test it out without having to connect to equipment.
The second tab is the one that I am having the problem with. the output array from the replace element appears to be starting at the index position of 1 rather than 0 but that is ok it is still show that the new data is placed in incrementing element locations. However the main array that I am trying to build that is suppose to take each new calculation and place it in the next index(row) does not ap
pear to be working or at least I am not getting any indication on the inidcator.
Basically what I am attempting to do is is gather some pulses from adevice for a minute, place the results for a calculation, so that it displays then do the same again the next minute, but put these result in the next row and so on until the specifiied time has expired and the loop exits. I need to have all results displayed and keep building the array(display until, the end of the test)Eventually I will have to include a min max section that displays the min and max values calculated, but that should be easy with the min max function.Actually I thought this should have been easy but, I gues I can not see the forest through the trees. Can any one help to slear this up for me.
Attachments:
regulation_tester_7_loops.vi ‏244 KB

I didn't really have time to dig in and understand your program in depth,
but I have a few tips for you that might things a bit easier:
- You use local variables excessively which really complicates things. Try
not to use them and it will make your life easier.
- If you flowchart the design (very similar to a dataflow diagram, keep in
mind!) you want to gather data, calculate a value from that data, store the
calculation in an array, and loop while the time is in a certain range. So
theres really not much need for a sequence as long as you get rid of the
local variables (sequences also complicate things)
- You loop again if timepassed+1 is still less than some constant. Rather
than messing with locals it seems so much easier to use a shiftregister (if
absolutely necessary) or in this case base it upon the number of iterations
of the loop. In this case it looks like "time passed" is the same thing as
the number of loop iterations, but I didn't check closely. There's an i
terminal in your whileloop to read for the number of iterations.
- After having simplified your design by eliminating unnecessary sequence
and local variables, you should be able to draw out the labview diagram.
Don't try to use the "insert into array" vis since theres no need. Each
iteration of your loop calculates a number which goes into the next position
of the array right? Pass your result outside the loop, and enable indexing
on the terminal so Labview automatically generates the array for you. If
your calculation is a function of previous data, then use a shift register
to keep previous values around.
I wish you luck. Post again if you have any questions. Without a more
detailed understanding of your task at hand it's kind of hard to post actual
code suggestions for you.
-joey
"nelsons" wrote in message
news:[email protected]...
> how do I create a 1d array that takes a single calculation and insert
> the result into the first row and then the next calculation the next
> time the loop passes that point and puts the results in thsecond row
> and so on until the loop is exited.
>
> The attached file is work inprogress, with some dummy data sp that I
> can test it out without having to connect to equipment.
> The second tab is the one that I am having the problem with. the
> output array from the replace element appears to be starting at the
> index position of 1 rather than 0 but that is ok it is still show that
> the new data is placed in incrementing element locations. However the
> main array that I am trying to build that is suppose to take each new
> calculation and place it in the next index(row) does not appear to be
> working or at least I am not getting any indication on the inidcator.
>
> Basically what I am attempting to do is is gather some pulses from
> adevice for a minute, place the results for a calculation, so that it
> displays then do the same again the next minute, but put these result
> in the next row and so on until the specifiied time has expired and
> the loop exits. I need to have all results displayed and keep building
> the array(display until, the end of the test)Eventually I will have to
> include a min max section that displays the min and max values
> calculated, but that should be easy with the min max function.Actually
> I thought this should have been easy but, I gues I can not see the
> forest through the trees. Can any one help to slear this up for me.

Change Management and Test Workbench for documentation

Hi,
I would like some clarification on the association between change requests and test workbench.
I'm going through scenarios such as creating a maintenance project, creating a task list and service message and then creating a transport request.
During these steps, I want to document the test results prior to migrating these transports into the production system.
My questions are - how do you link the maintenance project and also urgent corrections to a test procedure and documentation. It appears that by using solar01/solar02 and stwb_2/stwb_work, these tests are linked to a project and not necessarily a "change request"
I greatly appreciate if you can elaborate the association between the various areas a bit clearer for me.
Thanks!!!

You need to look for information on usage type "DI", "Development Infrastructure" or "NWDI" (all common abbreviations for the same thing). There were some very good presentations on NWDI at TechEd this year.
Here are some links to help documentation:
<a href="http://help.sap.com/saphelp_nw2004s/helpdata/en/63/7a4d40eae76f13e10000000a1550b0/frameset.htm">Administration of the Development Infrastructure</a>
<a href="http://www.sdn.sap.comhttp://www.sdn.sap.comhttp://www.sdn.sap.com/irj/sdn/developersguide">SDN NetWeaver Developers Guide</a>
Rich

Is there any way to search for a term using the Firefox search field, and have the results automatically open in a new tab?

Is there any way to search for a term using the Firefox search field, and have the results automatically open in a new tab? When there was support for Google Toolbar, I was able to do this; now, whenever I want to search for something, I have to open a new tab to do it, and cut-and-paste my search into the search field in the new tab. I used to be able to highlight, drag, and drop something into the search field and have it automatically open in a new tab. This is enough for me to switch to Chrome . . .

Set a preference to have searches from the Search Bar (upper right) automatically open all searches in a new tab
#type '''about:config''' in the URL/Location/Address bar and press the Enter key
#if you see a warning, accept it (promise to be careful)
#Filter = '''browser.search.openintab'''
#in the lower panel, double click the item (or right-click and choose "Toggle") to change the value to "true"
#close the about:config tab and test
#See:
#*For help with opening/using about:config, also see: http://kb.mozillazine.org/About:config
#*Also see: http://kb.mozillazine.org/About:config_entries (click on "Browser", scroll down to browser.search.openintab)
'''Search Bar''': http://support.mozilla.com/en-US/kb/Search+bar
'''If this reply solves your problem, please click "Solved It" next to this reply when <u>signed-in</u> to the forum.'''
About Google toolbar............
Google decided that they will no longer produce the Google Toolbar for Firefox 5 and newer version. It is best to move on to other alternatives than to try any "hacks" to the toolbar that may or may not perform in the future. Future versions of Google toolbar will only work with IE7-9. Google Toolbar is not available on any other browser, even Google's own browser.
*http://googletoolbarhelp.blogspot.com/2011/07/update-on-google-toolbar-for-firefox.html
*https://support.mozilla.com/en-US/kb/google-toolbar-not-compatible-firefox?s=google+toolbar&r=0&as=s
*http://www.google.com/support/toolbar/bin/answer.py?answer=1342452&topic=15356%29
*Google Toolbar 8 FAQ (IE only): https://www.google.com/support/toolbar/bin/answer.py?hl=en&answer=1111588
'''''To access your Google Bookmarks visit''''' www.google.com/bookmarks.
Alternatives:
*http://kb.mozillazine.org/Using_Google_Toolbar_features_without_toolbars
*https://addons.mozilla.org/en-US/firefox/addon/googlebar-lite/
*https://addons.mozilla.org/en-US/firefox/addon/gbookmarks-google-bookmarks-fo/

[svn] 1978: Bug: vendors. properties file which is used in vendor specific login commands was not being read properly and as a result some login related error messages were not being displayed correctly .

Revision: 1978
Author: [email protected]
Date: 2008-06-06 08:05:34 -0700 (Fri, 06 Jun 2008)
Log Message:
Bug: vendors.properties file which is used in vendor specific login commands was not being read properly and as a result some login related error messages were not being displayed correctly.
QA: Yes - we need automated tests to make sure that errors.properties and vendors.properties in BlazeDS/LCDS are loaded properly.
Doc: No
Modified Paths:
blazeds/branches/3.0.x/modules/common/src/java/flex/messaging/util/PropertyStringResource Loader.java
blazeds/branches/3.0.x/modules/opt/src/jrun/flex/messaging/security/JRunLoginCommand.java
blazeds/branches/3.0.x/modules/opt/src/tomcat/flex/messaging/security/TomcatLoginCommand. java

I have a lot of grief with this version of Windows Media Player.
It is very buggy and frustrating to use.
I have my Music library on a QNAP NAS, which is as reliable as they come.
System notifications make it not save changes. It also does not do a good job of interpreting albums and artists from folders. Changes to track names are not saved, nor are tracks moved to other albums, renamed albums, changes to genre, artist
or date. It separates and merges albums/tracks without sense or reason. Some changes I've made up to 4 times, then closed WMP and re-started my machine to check if it has/hasn't saved the changes. Often it has not.
This is the first time I've used WMP in this capacity, and I do not recommend it.
New service pack please.

Debug/Run for iOS simulator and Retina iPad

Even in the latest beta 2 releates, the dropdown for "Default Device" includes "iPad", "iPhone", "iPhone (Retina)" but does not include "iPad Retina". Seems like adding the "iPad Retina" woud be a matter of passing the correct flag to the iOS Simulator and should be quick and easy? When can we expect this?

Hi ,
Its a valid request. Please log an Enhancement request using the below link.
http://bugs.adobe.com/jira/login.jsp
Meanwhile you can try this workaround:
1.Open iOS simulator.
2.Choose Hardware->device from iOS simualator menu to the device on which you want to test your application.
3.Launch your application on iOS simulator from the Flash Builder.(Selecting the device on Flash Builder has no effect if the simulator is already running).
Thanks,
Sanjay

Minus and passing the result set

I have a query in a procedure....let us say "test.prc":
select A.VALUE from TABLE A
where A.VALUE_ID = get_rec.VALUE_ID minus
select B.VALUE from TABLE B
In the above query, I am passing the "get_rec.VALUE_ID" from a cursor above the query.
Now is there a way to capture the result set of the above minus operation and pass the result set to the calling sql program (called "call_test.sql")?
Thanks,
Chiru
Message was edited by:
Megastar_Chiru

I got what I was trying to do...
I have 1 more question though....I am printing out my output using dbms package from sql*plus...using the following command
dbms_output.put_line(nvl('Flex Value set Id : '||get_rec.flex_value_set_id,0)||' values that have no corresponding alias : ' || nvl(v_flex_val,0));
"get_rec.flex_value_set_id" gets passed in from my cursor above the dbms statement.
and it looks like below:
Flex Value set Id : 20118 values that have no corresponding alias : 00
Flex Value set Id : 20118 values that have no corresponding alias : 10
Flex Value set Id : 20118 values that have no corresponding alias : 11
Flex Value set Id : 20118 values that have no corresponding alias : 20
Flex Value set Id : 20118 values that have no corresponding alias : 30
Flex Value set Id : 20124 values that have no corresponding alias : Standard
Is there some way to neatly break when the value set id changes? ...ie., make it print output something like below:
Flex Value set Id : 20118
values that have no corresponding alias : 00
values that have no corresponding alias : 10
values that have no corresponding alias : 11
values that have no corresponding alias : 20
values that have no corresponding alias : 30
Flex Value set Id : 20124
values that have no corresponding alias : Standard
Thanks,
Chiru

Question of SAP Methodology of Implementation esp. System Testing and Test Script

Dear SAP Member,
As a very new and inexperienced customer to the SAP and the business. My company is preparing for the retail shop establishment which part of the preparation includes SAP implementation.
At first, we strongly believe SAP can fit and serve our business need well. Also, the standard methodology of implementation will be able to deliver the system with expected quality. However, the local implementor disappoint my firm with poor quality delivery and control that result in the perception of uncertainty of the system to be lived.
The methodology proposed by the implementor composed with
1) Preparation
2) Blueprint
3) Realization
a) Program development and unit test by vendor
b) Training
4) Final Preparation
a) Integration test by Users
b) Data conversion preparation
5) Go-Live and Support
My problem comes up with phase 4-5
Problem 1: Unit/functional test performed by implementor . For this activities, how could customer ensure that every single function has been developed or implemented according to the requirement and without error?
Problem 2: Vendor provides slot for integration test for 7 days. Is it normal practice that test can be done within this short period?
Problem 3: Does SAP methodology has the standard quality control, test enter and exit criteria and issue/incident management?
Problem 4: How should the standard test script look like? What i received from implementor was like functional list rather than script.
Problem 5: what should be step for conversion apart from the data preparation by users? The local implementor does not explain/elaborate the detailed activities.
Last but not least, as the customer do not satisfy with the SAP partner (local implementor quality). What should be the process for feedback as to prevent other new customer to face the same problem?
SK

SK,
Thamil has given his view. Here is another.
how could customer ensure that every single function has been developed or implemented according to the requirement and without error?
If this is an issue to you, you can insist that members of your test team participate in unit testing. You are, after all, the client, and it is your money being spent. As long as you can furnish testers, who are competent to evaluate unit testing scenarios, you can have them work with the vendor during unit testing.
Vendor provides slot for integration test for 7 days. Is it normal practice that test can be done within this short period?
It depends on what is being implemented. I have seen implementations which contained over a hundred test scenarios and over 2000 test scripts; each of which must be tested by multiple functional groups. 1 week is not enough to complete Integration testing in this case.
Also remember that it is necessary to allow time to correct 'bugs' found during integration testing, and then to re-test after the bugs are fixed. Except in the simplest of implementations, 1 week may not be enough to accommodate the bug fixes and retests.
Does SAP methodology has the standard quality control, test enter and exit criteria and issue/incident management?
Which 'SAP methodology' are you talking about? Bottom line, the client must insist that the vendor incorporate any methodologies that are required for his business. Don't assume that your vendor will automatically bring these items to the table, YOU may have to bring them to the table.
How should the standard test script look like? What I received from implementer was like functional list rather than script.
????? It should look like whatever you want it to look like. Many companies have existing templates. If your company doesn't have such a template, ask your vendor for one. Go over it together with him and make appropriate modifications that meet your business requirements.
what should be step for conversion apart from the data preparation by users? The local implementer does not explain/elaborate the detailed activities.
It is impossible to say at the beginning of the project. Sometime during realization, the client and the vendor will jointly develop a detailed cutover plan. More importantly, the client will develop a change management plan for the client company, in which all stakeholders in the client company will come to understand how and when ALL of the client's business processes will need to change, and to develop plans for all affected groups.
Best Regards,
DB49

Test simulation or Test run in program RFBIBL00

Hi,
I am trying to use the program RFBIBL00 for invoice posting...
I have filled the relevant data in the strucutres and populated the file...
Now i need to simulate/or do a test run to check the data is correct before the actual posting...
There is a checkbox for "Check File Only"... is this checkbox for the same purpose of simulation or test run?
Have anybody done the test run using this program, Do let me know
Also i am getting an error "Not able to open the file"....what could be the problem..(i have created a txt file and placed the same in the presentation server/desktop with some data..still there is an error)
Thanks
Shiva..

Hi,
Check file only checks the validity of the data in the file. The file must be sitting in app server.
Cheers.
...Reward if useful

Testmanagement: transport of business blueprints and test plans?

For the moment we have the following situation:
We have a 3 system landscape. (development system, test system and productive system)
On the the test system, the testmanagment module (testworkbench) was integrated. This is used by 5 test projects from extern SAP systems.
My question: Is there a possibility to transport the Businesses Blueprints and the test plans of the actual test projects into the productive system?

Hello Marc,
We have experienced similar problems. A transport of the test plan and copies of the test plans have resulted in us loosing status values and test notes.
I was informed it had to do with the fact the information is stored in the GUI. How I don't know, I am not a technical person.
I was wondering if you may have encountered the similar problems I have had above and found ways around it.
You can reach me at [email protected] as well.

Simulation and Testing my results

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