Adding FPGA reference causes problems

Hi,
I have a programme which runs on the RT engine and calls up an FPGA reference, samples data from this and then carries out some calculations on it. I'm currently trying to modify this to add more functionality, but have hit a problem. The picture attached is the original programme which works fine, but when I add another "Open FPGA VI reference" above the one shown, which is targeted to the same PXI 7833R card, but calls a different VI, it causes the original code to stop running properly. I haven't been able to track down the root of the problem, but it appears to be affecting the sampling of data in the original programme. I'm thinking it is something to do with timing as I haven't changed a single part of the programme except adding this extra FPGA reference, so all I think it could be affecting is the speed the programme runs at.
Does anyone know of any problems associated with opening two FPGA references at once?
Just in case you need to know, I'm running Labview 7.1, with a PXI 1042 chassis, PXI 8186 controller, PXI 7833R FPGA card and PXI 8461 CAN card.
Thanks,
Nick
Attachments:
working.jpg ‏73 KB

Nick,
As you add more code to the FPGA VI it will take longer to compile. If you get close to filling up the FPGA the compile time may increase significantly as the compiler spends more time to optimize the code that is generated to fit onto the FPGA.
Using large arrays on the front panel of the main VI or anywhere within your VIs will increase the size of the code and increase the compile time.
There are different ways to get around using large arrays but it is difficult to recommend a specific solution without knowing more about your application. All of these solutions will use the block memory available on the FPGA to store the data in one way or another. You should probably look at using FIFOs if you stream the data between the host and FPGA. Using FIFOs you can pass one data value at a time between host and FPGA, reading them from or writing them to the FIFO. You will need some form of handshaking to synchronize the host/FPGA communication.
An alternative is to use the DMA FIFOs which will further simplify the communication between host and FPGA.
If you want to pass blocks of data to the FPGA so that the data can be accessed repeatedly (like a lookup table) then you should use memory blocks on the FPGA to store your data. That provides random access by address to a predefined block of the memory on the FPGA.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Message Edited by Jeff Bohrer on 10-27-2009 02:21 PM
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Adding FPGA reference causes problems

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