FPGA reference gets invalid

Hi,
i am taking the reference of FPGA VI in RT code. passing it to sub VI. Sometimes i see link(wire) between FPGA reference and Sub VI is broke. What could be the reason? if i recreate the sub vi input it solves the problem.
Thank you,
Ranjith

If u do any changes in the FPGA code and complile,then ur FPGA reference will updated, but inside the subvis you placed the old reference controls only.so its showing broken arrow in all of your subvis.
Balaji PK (CLA)
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I get error 1055 "Object Reference Is Invalid" when I try to write to a property node

Hi, I'm trying to get these results to be displayed in two tables now, where I originally had them being displayed in just one. Outside of the attached vi, I can just copy the value property from one table to the other after this vi has run, and the table values appear properly. The problem with that is, that any table property I assign (changing background colours to be exact), is not considered part of the value property, and thus isn't copied when I copy the value from one to the other.
The thing I can't understand is that the second set of property nodes (at the bottom), give me the "Object Reference Is Invalid" when I added them. I've tried everything I can think of, but can see no logical reason why I get that error for those two, while I don't get the error for the top two (not wired to constants).
Any help on this would be much appreciated. Thanks
Geoff
Attachments:
Table Display Testing.vi ‏396 KB

The logical reason that you're getting that error is that you are not passing in a reference to Table In Two. The control is not wired to the connector pane so you are not getting a reference from the calling VI.

Why does opening and closing FPGA references increase Windows XP handles by 3?

Hello.
We run a test system here that uses TestStand to communicate
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after a particular VI was run 100,000 times, the number of handles in Windows XP Task
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Appreciate any help here. Thanks.
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could be related to this known issue--
FPGA FIFO reset behavior—When you use an FPGA target
emulator, FPGA FIFOs reset when the VI is stopped and then started
again. When you use an FPGA target with Interactive Front Panel
Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and
then started again. To reset the FIFO, right-click the FPGA target in
the Project Explorer window and select Download
from the shortcut menu. When you control an FPGA VI using Programmatic
FPGA Interface Communication, use the Close FPGA VI Reference function
with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs
see Knowledgebase
Also remeber to load the FPGA Read/Write VI's dynamically from testStand and dump them after. Thechange to the data type causes the vi to need to recompile so it can't stay in memory if you need different types of data.
Message Edited by Jeff Bohrer on 10-27-2009 02:21 PM
Jeff

When do VI and queue references become invalid?

Hi all,
I have a fairly complicated problem, so please bear with me.
1) I have a reentrant SubVI (let's call it VI "Assign") that has an input cluster of (VI ref, queue ref) (let's call the cluster type "Refs"). If the VI ref is invalid (first execution), the VI ref and queue ref are assigned values and are passed on as an output cluster of same type. (The VI does other things too, but for simplicity only this is important.)
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3) VI "Store" is called by multiple non-reentrant VIs, so the local variables of VI "Assign" retain their values (Has been tested and verified to retain their values). The VI causing the problem in this case is a template VI of which multiple copies are launched (let's call it VI "Template").
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Unfortunately I cannot include the code.
Thank you whoever is able to make sense of this.
Christie

Christie wrote:
Hi all,
I have a fairly complicated problem, so please bear with me.
1) I have a reentrant SubVI (let's call it VI "Assign") that has an input cluster of (VI ref, queue ref) (let's call the cluster type "Refs"). If the VI ref is invalid (first execution), the VI ref and queue ref are assigned values and are passed on as an output cluster of same type. (The VI does other things too, but for simplicity only this is important.)
2) The VI that calls VI "Assign" (let's call it VI "Store") is not reentrant and has a local variable of type "Refs" that is wired to the input and output of VI "Assign". This VI effectively stores the references. The references returned by VI "Assign" are always valid right after the call, but after the problem condition described below, they are invalid at the start of all calls before they are passed to VI "Assign".
3) VI "Store" is called by multiple non-reentrant VIs, so the local variables of VI "Assign" retain their values (Has been tested and verified to retain their values). The VI causing the problem in this case is a template VI of which multiple copies are launched (let's call it VI "Template").
The problem is that the moment an instance of VI "Template" is closed, the queue reference becomes invalid, although the actual variant value of the reference remains the same. The VI ref can become invalid or not, depending on small changes, but is always reproducible. I assume there must be some similarity between VI and queue refs. After spending some time researching, the Labview help states for the Open VI Ref component "If you do not close this reference, it closes automatically after the top-level VI associated with this function executes." In this case I assumed it means that the moment the reentrant VI "Assign" finishes, the references will get cleared ?? So I made a non-reentrant VI (let's call it VI "NR Assign") that only assigns values to the references and VI "Assign" now calls this VI (It effectively does what I described VI "Assign" does). I keep this VI alive by using it in a VI which never terminates and since it never terminates, the references should never become invalid. Anyone still following? This didn't solve the problem though. If I reproduce the same scenario using only one instance of the template VI, it works just fine. Furthermore, the VI and queue references are never closed, to aid analysis of the problem. Can anyone shine some light on what happens when a template VI terminates? Could this be the problem?
Unfortunately I cannot include the code.
Thank you whoever is able to make sense of this.
Christie
All LabVIEW refnums do get deallocated automatically when the top-level VI in whose hierarchy the refnum was created goes idle (stops executing). You will have to make sure that the creation of a refnum is done inside a VI hierarchy that stays running for the entire time you want to use that refnum.
Rolf Kalbermatter
Message Edited by rolfk on 06-27-2007 11:52 AM
Rolf Kalbermatter
CIT Engineering Netherlands
a division of Test & Measurement Solutions

Error code 63003..while running a FPGA prog on Host PC using FPGA reference VI

Hi,
when i run my FPGA program on HOST PC using a FPGA reference vi on windows platform, I get an error code 63003 (FPGA bit file out of date). When I go back, recompile and run the FPGA program on the FPGA target, then shut it and come back to HOST PC and run my application with FRGA Open refence vi, it runs with out any error! Does any one know why I get that error code 63003

This error means that the VI which is downloaded to the FPGA was changed on the host/development system, but has not been recompiled. By recompiling it you resolve this problem.
When a LabVIEW FPGA VI is compiled for the FPGA, the bit stream, which will be downloaded to the FPGA, is stored in the VI file. When LabVIEW RT or LabVIEW Windows attempts to download the bit stream to the RIO card, it makes sure the bit stream corresponds to the VI source code in the same file. This is necessary so that the host application can properly communicate with the VI on the FPGA. If the two are not the same, this error is generated from the Open FPGA VI Reference function in the host application.
Christian L
NI Consulting Services
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Error: demo.model.AppModule: Application module demo.model.AppModule has a view instance EmpByEmail1 that references an invalid view object.

Error: demo.model.AppModule: Application module demo.model.AppModule has a view instance EmpByEmail1 that references an invalid view object.
intially i created view object named EmpByEmail.........for that EmpByEmail1 is created in datacontrols....i deleted EmpByEmail in demo.model by mistake and i created again with same name EmpBYEmail another view object...again another EmpByEmail2 is created in datacontrols.....
while i am running i am getting following error:::::::
Error: demo.model.AppModule: Application module demo.model.AppModule has a view instance EmpByEmail1 that references an invalid view object.

Hi,
Please seasrch for the EmpByEmail1 file in ur project and remove all the details in the Page Def and UI and then try again.
Due to the EmpByEmail1 existance in page Def this may occur . It may help , still if it was not working then I am sorry for that.

On cRIO-9033, property node: Owning VI Reference is Invalid

I am starring for the first time to work with a UI on cRIO-9033. The code I am trying to adapt to work on the RT is working on Windows just fine. But when I put it on the RT it throws errors. I looked through the code and I kept getting error 1026 Reference is No Longer Valid. I made a very simple code to try and run (as linked below), and it throws the same error.
When I probe the error coming out of the VI Property Node: Panel, it gives me an Invalid Reference Error. Nothing closed the reference and the VI is obviously still running and in memory since this is the VI. I'm not sure what is wrong. Could it be that I am running it from development environment? Or is this a quirk with programming in Linux?
Attachments:
Simpler UI.vi ‏16 KB

I found another bug. You just to follow my instructions if you don't mind
Open the attached code
Run it. It should work fine
Move anything on the front panel and save it
Run it. You should get errors.
I'm not sure what is wrong but I can reproduce the problem over here.
BEFORE IMAGE
AFTER IMAGE
notice the I moved error out 2
Actually on my more complicated example the property node giving the panel references passes invalid references all the time. Not just when I resave it.
Attachments:
Simpler UI.vi ‏19 KB

LV2012 crashes when opening LV2010 project containing OOP and dynamic FPGA references

I have a project that was written under LV2010 and has no problems that I am aware of. This project contains OOP and dynamic FPGA references. I am trying to upgrade this project to LV2012. When opening this project under LV2012 (or any subVI containing OOP) I get an error message, as shown in the attached screenshot. Has anyone else observed this problem? I haven't found any relevant postings on this forum yet.
My project is quite large, with many accessors.
Thank you for any assistance you can offer.
Attachments:
LV2012_Crash.PNG ‏22 KB

Thank you for your response, but the Discussion Forums link that you provided refers to a problem that occurs when exiting a running executable. My problem is different. I am simply opening up a LV2010 project using LV2012. No running of my program is involved.
Anyway, after several days of work, I narrowed down the cause of the LabVIEW crash. My code contained a Disable structure, and within that Disable structure there was a subVI that had an unwired object terminal (set to dynamic dispatch). Deleting the subVI in the Disable structure eliminated the LabVIEW crashing. Weird behavior.

Why XControl's reference is invalid?

There are 60 XControls on front panel.I get their reference by a subvi and then output their label text by property node.It's ok when vi run in labview 8.5 IDE.Then I build the program to exe file.The refrence is invalid when I run the exe file .So what's wrong about the exe file?
Thanks!

I hava sloved my problem .The problem occured when a common reference translated into special reference .Jsut like the image:
When running the exe file,CargoBlock reference is invalid.But I change the method that gets CargoBlock reference ,as follows:
The problem disappears...

Open FPGA reference - slow?

I'm trying to do some data acquisition through a cRIO 9101 attached to DI, DO and AI modules. Right now, I have something like a Read AI VI in my cRIO application that opens the FPGA reference, reads the control (using the read control node), then closes the FPGA reference and returns the read value to the calling VI. My issue is that this seems mindbogglingly slow.
I use this VI and the corresponding DI and DO VIs that are pretty mucht he same internally in a handful of places throughout my code and at least in one spot where I've timed it, it takes something like one full second to run this VI. The culprit seems to be the open FPGA reference VI.
At this point, can anyone suggest what I'm doing wrong?
Is this the right way to go about this, given that my access to the FPGA needs to be fairly scattered throughout my code?
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An alternative that I've got going right now is to use the first call VI to only use the open FPGA reference once, then store the reference in a shift register.
Both of these soultiuons create some issues with closing the FPGA reference. Can anyone comment if closing the FPGA reference is really all that necessary?
Thanks,
Chris

My VI is fairly complex, I do single reads and writes in various locations throughout the code, but never repeatedly in rapid succession. To facilitate this, I had a subVI that just reads analog values from the FPGA and it is within this subVI that I had the sequence of Initialize FPGA ref. --> read --> close FPGA ref. This was the initial solution that was giving me trouble, each call to this sub VI would take a very long time.
My solution right now is to initialize the FPGA reference once at the start of the application and store it in a global, then use that reference every time I do a read/write. This leads to not closing the reference until the application is done, which, in my application, really doesn't happen unless there's a system reboot, power failure, etc. So at the end of my application frequently, the reference will not get closed.
I assume that opening the reference does not store any state information that would survive a reboot (i.e. storing something in flash), so not closing the reference shouldn't be an issue. If anyone has any information to the contrary, please let me know.
Thanks,
Chris

Adding FPGA reference causes problems

Hi,
I have a programme which runs on the RT engine and calls up an FPGA reference, samples data from this and then carries out some calculations on it. I'm currently trying to modify this to add more functionality, but have hit a problem. The picture attached is the original programme which works fine, but when I add another "Open FPGA VI reference" above the one shown, which is targeted to the same PXI 7833R card, but calls a different VI, it causes the original code to stop running properly. I haven't been able to track down the root of the problem, but it appears to be affecting the sampling of data in the original programme. I'm thinking it is something to do with timing as I haven't changed a single part of the programme except adding this extra FPGA reference, so all I think it could be affecting is the speed the programme runs at.
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Just in case you need to know, I'm running Labview 7.1, with a PXI 1042 chassis, PXI 8186 controller, PXI 7833R FPGA card and PXI 8461 CAN card.
Thanks,
Nick
Attachments:
working.jpg ‏73 KB

Nick,
As you add more code to the FPGA VI it will take longer to compile. If you get close to filling up the FPGA the compile time may increase significantly as the compiler spends more time to optimize the code that is generated to fit onto the FPGA.
Using large arrays on the front panel of the main VI or anywhere within your VIs will increase the size of the code and increase the compile time.
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An alternative is to use the DMA FIFOs which will further simplify the communication between host and FPGA.
If you want to pass blocks of data to the FPGA so that the data can be accessed repeatedly (like a lookup table) then you should use memory blocks on the FPGA to store your data. That provides random access by address to a predefined block of the memory on the FPGA.
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
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to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense

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How to close FPGA reference out from different while loop

Hi Friends,
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Rohit,
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Please mark this as the correct answer to award points if it is or if you read it and it helped you.
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FPGA reference gets invalid

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