AXI Stream Data FIFO sends data automatically

Question

Hi all!
I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and connect them to the PS on my Zynq board. So far, I've managed to sucessfully create AXI DMA to send data from PS to PL AXI Stream Data FIFO and vice versa. However, if I expand my PL with a custom IP with AXI Stream interface and connect it to the AXI Stream slave interface of my AXI Stream Data FIFO to send data to FIFO, my linux application gets stuck when trying to read the data of FIFO via DMA. After some simulations and debugs I figured out, that my FIFO is empty and cause the stuck of my application, because DMA waits for data.
For this reason I seperated my custom IP and FIFO from the DMA to test and debug only the connection between custom IP and FIFO without the influence of DMA. Thus the master interface of the fifo is not connected. Accordingly every second my custom IP shall properly open a transfer and send 10 values of 32 bit to FIFO where it should be stored and not send.
However, debugging this PL with ILA core ends with the result, that my FIFO stops to be ready-to-receive after receiving and storing 3 values of 32bit. Then it waits until it receives a high TLAST signal of custom IP. During this waiting period it does not store my remaining values. After TLAST gets high with the 10th 32-bit value, FIFO´s signal TVALID is set instantly to high and FIFO starts to submit the data. This is the point where I get confused. Why does FIFO starts to transmit when there is no receiver connected to FIFO´s AXI Stream master interface? From my level of knowledge FIFO needs the signal TREADY high from a slave peripheral to starts the transmission.
I believe this behavoiur is the reason of not storing the values in FIFO.
Hopefully somebody knows whats going wrong here or what I am doing wrong. I really appreciate any help because I have been trying 2 weeks to solve this problem without any success. It is really frustrating...
Please see attachments for better understanding. If you need further information let me know.
Best regards,
timmaexd
 

Answer 1

Thanks for replying and checking my diagrams! Fortunately, I could solve the problem.
After you gave me the advice to check m_tready, I figured out that this signal was constantly set to high. This was caused by VCC, which was connected automatically with m_tready, after synthesis.
Thus I connected DMA with FIFO to replace VCC with DMA and consequently data was stored correctly.