AXI4 memory mapped slave user logic implementation

Question

hi, I'm using a Spartan6 and the EDK.
I'm trying to write data via PCIe/AXI to a third party IP core, and read data of this IP core. The connection looks like this:
PCIe/AXI MM bridge <> AXI Interconnect <> AXI_MM_Slave <> two instances of the 3rd_party_IP_core
I want to read/write 128 bits. I created an AXI4 memory mapped slave with two address spaces with the CIP Wizard.
Now I'd like this AXI slave to read the data from the bus, and forward it to an output : std_logic_vector(127 downto 0), and read data of an input : std_logic_vector(127 downto 0) and write this data to the AXI bus.
I don't know how to use the IPIC signals the CIP Wizard created, to do this. As I want to read/write 128 bits while the Bus2IP_data and IP2Bus_data is only 32 bits wide, I don't know how to manage this. Could anyone please help me with some VHDL-code?
Thanks and regards,
Fabian

Answer 1

As per my understanding
It may  be  possible  If one person manages all service desk operations and that person have windows user id with userid "SERVICEDESK ".
It is not possible for several users to have same userid in Active directory
Integration of portal with windows userid possible whith same userid.
we can see some other inputs also
Koti Reddy