PCIe/AXI to user logic addressing

Question

Hi,
I’m using a Spartan-6 XC6SLX45T-FGG484-2 FPGA and I’m using the Xilinx Platform Studio.
I want a PCIe host pc to communicate with two instances of a third party IP core via AXI4 memory mapped.
The host PC performs PCIe write and read transactions. The AXI slave responds to these transactions:
The AXI slave receives the data the host pc sent, and forwards it to the third party IP core, for a write request. For a read request, the AXI slave reads the data from the third party IP core, and sends it via AXI to the PCIe host pc.
My design looks like this:
PCIe/AXI MM bridge <> AXI Interconnect <> AXI_to_User_Logic <> 3rd_party_IP_core_0
                                                                                                                    <> 3rd_party_IP_core_1
AXI_to_User_Logic is an AXI4 memory mapped slave with two address spaces, that was created with the Create & Import Peripheral Wizard.
My first question is:
I think the PCIe/AXI bridge should be the AXI Master, so do I need to connect only the M_AXI to the AXI bus, or do I have to connect S_AXI and/or S_AXI_CTL as well?
The next question is: how to set the addresses?
I’m not sure whether I understood how to do the addressing, so I’d like someone to verify that the addressing I made is right. If it’s wrong, please show me how it has to be done.
I want to send 32 bytes to each AXI address space of the AXI slave and read 32 bytes from each AXI address space of the Slave.
Addresses of PCIe/AXI bridge IP core:
PCIe/AXI bridge: AXI Device Base Address (C_Baseaddr) = ?
PCIe/AXI bridge: AXI Device High Address (C_Highaddr) = ?
These Addresses can only be set in the PCIe/AXI bridge, not in the Slave. What do they mean? How should they be set?
Write and Read 32 Bytes to/from two AXI address spaces means: PCIe BAR size = 32 Bytes *2*2 = 128 Bytes (?).
128 = 2^7 --> PCIe BAR needs the lower 7 Bits to be 0 --> The bridge’s parameter C_PCIEBAR _LEN_0 = 7
The PCIe BAR gets determined by the configuration software.
Do I need an AXI BAR in the bridge? I don’t think so, as I only want to use the AXI Master Interface, right?
PCIe/AXI bridge: AXI Base Address 0 (C_AXIBAR_0) = ?
PCIe/AXI bridge: AXI High Address 0 (C_AXIBAR_HIGHADDR_0) = ?
PCIe BAR 0 mapped from AXI BAR 0 (C_AXIBAR2PCIEBAR_0) = ?
This BAR is only needed, if the endpoint (AXI/PCIe bridge) wants to initiate a transaction to the root port (that’s what I read about it, in the Xilinx support forum). So I don’t need this, right?
AXI BAR 0 mapped from PCIe BAR 0 (C_PCIEBAR2AXIBAR_0) = 0000 0000
Addresses of the User Logic IP core:
AXI_to_User_Logic_0:Mem0    Base Address = 0000 0000
AXI_to_User_Logic_0:Mem0    High Address = 0000 001F
AXI_to_User_Logic_0:Mem1    Base Address = 0000 0020
AXI_to_User_Logic_0:Mem1    High Address = 0000 003F
--> Both address spaces are 32 Bytes.
Let’s say the configuration software set the PCIe BAR0 to 0x0100 0000.
If the User_logic’s BARs and the PCIEBAR2AXIBARs are configured like above, I can access the second axi address space by performing a PCIe transaction with PCIe Baseaddress = 0100 0020 which will result in an AXI request with address = 0x00000020. Is this right?
I appreciate any help,
Fabian

Answer 1

interconnect is when you have one master, multiple slaves or multiple masters, single slave or any combination of NxM connectivity. If you have a single master and a single slave then there is no need for an interconnect and you can connect your master to the slave directly.
If you want a master example, you can do "tools|create&package ip|create new ip" and create an ip with master interface. Then you can add your master state machine/controller inside.
Also keep in mind that if you want your master to talk to your own slave and DDR you need to either have two master interface in your IP block or add an interconnect to demux your master to two separate slaves.