Can we simulate a rs 232 bus using an fpga module
i would like to replace a communication bus (UART, baud rate - 200K) with FPGA card(7831). is it possible to simulate this one???
Hi,
Yes, check out the RS-232 Interface Using the LabVIEW FPGA module on the Developer Zone. You can also find additional examples and tutorials for the LabVIEW FPGA Module here. You may need to modify the application to get the specific rate that you need but that rate is attainable.
Good Luck
Mike
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I am working on implementing dynamic systems modeled ordinary differential equations on PXI-7811R FPGA using labview FPGA. Is there any body who can help me how to implement differential equation on PXI devices uding Labview FPGA, please? Is there any integrator in Labview FPGA, module. I used Discrete Integerator in LAbview FPGA module in Maths palette, but i hesistated if it really works . I really appreciate your help,
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http://search.ni.com/nisearch/app/main/p/bot/no/ap/tech/lang/en/pg/1/sn/ssnav:ipn/q/differential%20e...
Below is a link that you can review to better understand the functionality of the discrete integrator should you choose to go that route:
http://zone.ni.com/reference/en-XX/help/371599B-01/lvfpga/discrete_normalized_integrator/
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Hi!
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My test bench:
module VGA_top_tb(
reg clk = 1'b0;
reg reset = 1'b0;
initial begin
#5 reset = 1;
#30 reset = 0;
end
always begin
#5 clk = !clk;
end
VGA_top VGA_DUT(
//inputs
.clk (clk),
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.down_btn (1'b0),
.left_btn (1'b0),
.right_btn (1'b0),
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.green (),
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.vs ()
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`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "DCM,clk_wiz_v3_6,{component_name=DCM,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module DCM
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
// Input buffering
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(.O (clkin1),
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wire clkfbout;
wire clkfbout_buf;
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wire clkout0b_unused;
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wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("HIGH"),
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.CLKFBOUT_MULT (20),
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.CLKOUT0_DIVIDE (20),
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.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (50),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
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.LOCKED (LOCKED),
.PWRDWN (1'b0),
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// Output buffering
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
endmodule
Thanks!Hi Gabor!
Thanks for your reply. I have noticed your observation that the naming of the DCM is different in the error message. I have re-name it before I post it in here but nothing changed. I have also tried "re-run all" to start the simulation but with no success.
In the end, I have manually removed the DCM instance and created a new one with the same parameters. This seems to solve the issue. Now works both on the board and in simulations. I'm not entirely sure what was the problem in order to avoid it next time.
Thanks for your help! -
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