Can't simulate Clocking Wizard in ISE 14.7

Question

Hi!
I have developed a simple design for a VGA module where I need to produce a 40Mhz clock out of 100Mhz input for an Artix-7 (XC7A100T-CSG324) on an Digilent Nexys4 evaluation board. In order to aquire this clock I have used a Clock Wizard for a DCM. I have synthesise the desing, upload the bit file and everything works fine, as expected on the board.
I would like to extend the design and add more functionality. I order to achieve this, I need a test bench in parallel that will help me to continue the work. I have started by implementing the simplest test bech just to make sure it works. iSim doesn't want to start and the errors suggests that it doesn't see all the ports of the DCM:
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 131: Module <DCM_default> does not have a port named <CLK_IN1>.
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 133: Module <DCM_default> does not have a port named <CLK_OUT1>.
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 134: Module <DCM_default> does not have a port named <CLK_OUT2>.
ERROR:HDLCompiler:25 - "C:/Users/Popa/Desktop/FPGA/NEXYS4/DESIGNS/VGA/VGA_top.v" Line 136: Module <DCM_default> does not have a port named <RESET>.
ERROR:Simulator:778 - Static elaboration of top level Verilog design unit(s) in library work failed
 I don't understand what I'm doing wrong...the same code synthesize and produce succesfully the bit file and everything works fine but I can't simulate it. I'm using ISE WebPACK Design 14.7 (P.20131013).
My test bench:
module VGA_top_tb(
reg clk = 1'b0;
reg reset = 1'b0;
initial begin
#5 reset = 1;
#30 reset = 0;
end
always begin
#5 clk = !clk;
end
VGA_top VGA_DUT(
//inputs
.clk (clk),
.reset_h (reset),
.up_btn (1'b0),
.down_btn (1'b0),
.left_btn (1'b0),
.right_btn (1'b0),
//outputs
.red (),
.blue (),
.green (),
.hs (),
.vs ()
endmodule
DCM code:
`timescale 1ps/1ps
(* CORE_GENERATION_INFO = "DCM,clk_wiz_v3_6,{component_name=DCM,use_phase_alignment=true,use_min_o_jitter=true,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,feedback_source=FDBK_AUTO,primtype_sel=MMCM_ADV,num_out_clk=2,clkin1_period=10.000,clkin2_period=25.0,use_power_down=false,use_reset=true,use_locked=true,use_inclk_stopped=false,use_status=false,use_freeze=false,use_clk_valid=false,feedback_type=SINGLE,clock_mgr_type=MANUAL,manual_override=false}" *)
module DCM
(// Clock in ports
input CLK_IN1,
// Clock out ports
output CLK_OUT1,
output CLK_OUT2,
// Status and control signals
input RESET,
output LOCKED
// Input buffering
IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));
// Clocking primitive
// Instantiation of the MMCM primitive
// * Unused inputs are tied off
// * Unused outputs are labeled unused
wire [15:0] do_unused;
wire drdy_unused;
wire psdone_unused;
wire clkfbout;
wire clkfbout_buf;
wire clkfboutb_unused;
wire clkout0b_unused;
wire clkout1b_unused;
wire clkout2_unused;
wire clkout2b_unused;
wire clkout3_unused;
wire clkout3b_unused;
wire clkout4_unused;
wire clkout5_unused;
wire clkout6_unused;
wire clkfbstopped_unused;
wire clkinstopped_unused;
PLLE2_ADV
#(.BANDWIDTH ("HIGH"),
.COMPENSATION ("ZHOLD"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT (20),
.CLKFBOUT_PHASE (0.000),
.CLKOUT0_DIVIDE (20),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT1_DIVIDE (50),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKIN1_PERIOD (10.000),
.REF_JITTER1 (0.010))
plle2_adv_inst
// Output clocks
(.CLKFBOUT (clkfbout),
.CLKOUT0 (clkout0),
.CLKOUT1 (clkout1),
.CLKOUT2 (clkout2_unused),
.CLKOUT3 (clkout3_unused),
.CLKOUT4 (clkout4_unused),
.CLKOUT5 (clkout5_unused),
// Input clock control
.CLKFBIN (clkfbout_buf),
.CLKIN1 (clkin1),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (do_unused),
.DRDY (drdy_unused),
.DWE (1'b0),
// Other control and status signals
.LOCKED (LOCKED),
.PWRDWN (1'b0),
.RST (RESET));
// Output buffering
BUFG clkf_buf
(.O (clkfbout_buf),
.I (clkfbout));
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkout0));
BUFG clkout2_buf
(.O (CLK_OUT2),
.I (clkout1));
endmodule
Thanks!

Answer 1

Hi Gabor!
Thanks for your reply. I have noticed your observation that the naming of the DCM is different in the error message. I have re-name it before I post it in here but nothing changed. I have also tried "re-run all" to start the simulation but with no success. 
In the end, I have manually removed the DCM instance and created a new one with the same parameters. This seems to solve the issue. Now works both on the board and in simulations. I'm not entirely sure what was the problem in order to avoid it next time.
Thanks for your help!