CIC decimation and Compensation filter

Hi,
I have to implement a three stage multirate filter in FPGA where Stage1 is a CIC filter, Stage2 and Stage3 are the FIR filters. I have generated the filter parameters of all the stages using the 'Multistage Multirate Filter Design Express VI'. According to that Stage1 decimates the signal 4 times, Stage2 and 3 decimates 2 times. So an overall decimation factor of 16.
I used an FM band of 4 MHz with an IQ rate of 5MS/s as my input to the CIC filter. The CIC filter works fine and decimates the signal to an IQ rate of 1.25 MS/s. I then used those decimated signal values and fed it to the 'DFD MRate Filtering for Single block VI' , which decimates the signal further to an IQ rate of 625 kHz and gives the correct output as desired.
I did the same with 'FIR filter VI' using the coefficients generated by the' Multistage Multirate Filter Design Express VI' for stage2 and decimated it 2 times using 'Decimate (continuous) VI'. It should give me the same output as obtained by 'DFD MRate Filtering for Single block VI'. The frequency response of both FIR and MRate filter are the same but their filtered outputs don't match.
Any suggestions why am I not getting the desired output? I have attached the VI of my labview code. Kindly have a look.
Thanks
Attachments:
test.vi ‏123 KB

Hello
I am building a digital down converter in LabVIEW. I am not able to figure out if my output is correct ( Inphase and Quadrature components). Am I on the right path? Please find attached the VI I have been working on.
Thank you.
Attachments:
ddcnew5.vi ‏267 KB

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