Clock Domain Crossing with FIFO

Hi,
I have a project for Spartan 6 xlx16. In this project I have:
- clk_in: 20 MHz from an external Quart
This clk_in (20 MHz) has the followin path:
- 20 MHz -> Clock Wizard -> 20 MHZ -> Clock Wizard -> Out1: 22 MHz, Out2: 44 MHz.
The 22 MHz is used to acquire data, and 44 MHz is used to transmit the data. So I used a FIFO:
en_fifo_nempty <= not en_fifo_empty;
my_fifo : fifo_generator_v9_3
Port map (
rst => reset_ien,
wr_clk => clk22,
wr_en => '1',
din => data_in,
rd_clk => clk44,
rd_en => en_fifo_nempty,
dout => data_out,
full => open,
empty => en_fifo_empty);
I have a analog channel where I can compare in parallel the original data with Acquired + Transmitted Data. I synthesize one and I notice that Data bit 7 is not stable. Make some changes Data bit 4 in not stable. Some more changes data bit 5.. and son on.
What am I missing here? What am I'm doing wrong? In *ucf file I have no special constrains (only clock constrains).
There are no timing/setup errors.
PS: I'm not allowed to change the Acquisition and Transmission Modules so I have to stick to 22 MHz and 44 MHz.
Thaks,
Paul

The input data is aquired synchronous from an ADC and processed with the 22 MHz (digital filtering, adder ...). ADC clock is generated dividing the 22 MHz clock with /2 ( simple clock divider).
With 20 MHz and 40 MHz everything is ok.
I have to increase the dynamic of the system with 10% and not allowed to change some VHDL modules so I tried this overclocking (ADC can work at way higher frequencies). With 22 MHz and 44 MHz and absolutely no error from ISE Tool it doesn't work correctly any more.

Similar Messages

Clock domain crossing FIFO sanity check

Hi all,
I am having an issue with producing a one clock cycle wide pulse output. I have dealt with crossing clock domains before but I just want to make sure I am not doing anything wrong.
I have two clock domains that are mesochronous, both are 250MHz from two different external devices that are deskewed in a DCM.
I generate a 1 clock cycle wide pulse from clock domain 1 periodically. I need this pulse to cross the domain coherently into clock domain 2 so that the period remains the same. In other words the latency from crossing clock domains must have a a constant latency (the amount of latency does not matter as long as it is the same all the time).
I am using a coregen generated asynchronous block RAM FIFO. The write enable is the pulse output from clock domain 1 and the empty flag of the FIFO is the output pulse (except I negate it and register the output in an IOB FF clocked with clock domain 2s clock). The output FF is actually a FDCPE, since it is necessary on power up to send an asynchronous '1' to the device. Once the asynchronous '1' is outputted, it is cleared and never used again. I am guessing that an FDCPE primitive will act the same as a FF.
Here is the issue:
On power up, if it works, it will continue to work at all temperatures for as along as the system is powered on. If on power up it does not work, it will continue to not work for as long as the system is powered on. I am assuming this is a power-on phase issue. Would this have something to do with how I am crossing the clock domains or should I look elsewhere?
When I say it does not work I mean:
Clock domain 1 is from an ADC and clock domain 2 is from a device similar to a DAC. The output of the DAC feeds back into the ADC. When it does work, the output I create from the DAC is coherently read from the ADC. When it does not work, it looks as if the DAC output is started at different clock cycles (multiple phase shifts). This is why I am assuming that it is due to signal coherency, but we have used this scheme for crossing clock domains multiple times and it has always worked without any issues.
Sorry if this is not enough information.
Thanks

I don't entirely understand the description of the problem you are seeing - we need more context for that. But I will address the clock crossing.
I don't see anything fundamentally wrong with the clock crossing mechanism you are describing. However, it is VERY expensive for what you are using it for. In fact, even though you are using a clock crossing FIFO, you aren't actually using the storage of the FIFO - you are just using the address counters and full/empty flag generation (which is implemented in fabric logic), and completely ignoring/wasting the RAM.
There are many simple circuits for doing this clock crossing. As long as you can ensure that you will never get one pulse less than 3 (maybe even 2) after the previous one, then the circuit shown below (a toggle event synchronizer) is simple cheap and effective
This circuit takes your pulse event on the source clock domain, converts it into a toggle event, which is then synchronized through a two stage synchronizer and then edge detected in the destination domain.
You don't say what tool you are using (Vivado or ISE) - in either tool it will need some constraints.
In Vivado, you should set the ASYNC_REG property on the two middle flip-flops
set_property ASYNC_REG TRUE [get_cells {signal_meta_reg signal_dst_reg}]
You will also need some sort of exception on the clock crossing (since all clocks in Vivado are related by default). My preferred one is
set_max_delay -datapath_only 4 -from [get_cells event_toggle_reg] -to [get_cells signal_meta_reg]
You should still use this even though both clocks are 4ns periods (so the requirement will end up being 4ns anyway) but the -datapath_only flag tells the tools not to analyze the clock insertion... Furthermore, on this synchronizer, a max_delay isn't technically needed (since there is only one signal being synchronized), so you could set the path as being false, but it is good habit to use this constraint anyway, since other synchronizers need it.
If you can't guarantee that there are 2 clocks between events, then you can use a simple Gray code counter on the source domain to count events, and send the count to the destination side, which will generate one output pulse for each count received - this is basically what the logic in the FIFO is doing, but without carrying around the useless RAM.
And, by the way, if you are going to stick to the FIFO, why not use a distributed RAM based FIFO - you won't need to waste the block RAM... If you make it 64x1, then you will only waste two LUTs for the useless RAM instead of an entire block RAM.
Not that this matters, but you say that the clocks are mesochronous - are they really? To be mesochronous, they need to derive from the same oscillator; they may go through very different paths, but they must come from the same frequency source. Merely both being 250MHz does not make them mesochronous (but, as I say, that doesn't matter for this clock crosser ).
As for the rest of it - I don't think the clock crossing is the source of your problem. Its vaguely possible that you are messing up the FIFO logic by giving it a pulse too close to the deassertion of the reset; the built-in FIFOs have a requirement that the WR_EN not be asserted within a handful of clocks after the deassertion of rst. But you say you are using the block RAM based one, which probably doesn't need this. So its probably not the clock crosser...
Avrum

Multiple clock domains each with clock mulitplexing. Solve warning (Place 30-568])

My design can be partitioned in several clock regions (up to 20 for now). In each region I've instantiated a PLL and each PLL generates 4 clocks. I need to multiplex these 4 clocks per each region and to clock gate the output based on a signal in the fabric logic.
I know the a proper way of doing it would be to use 3 BUFGMUX components followed by a BUFGCE, however this has issues:
1) Even if I have a V2000 Virtex7 FPGA, I can only use up to 32 BUFGs because of the placement constraints.
2) Assuming I could give up and reduce the number of clock regions, it's impossible to place all 4 BUFGs in adjacent sites, therefore implementation fails unless I specify DEDICATED_CLOCK_ROUTE FALSE. I would prefer avoiding this option, because the design is fairly complex and Vivado struggles to meet timing already.
I tried to multiplex the the first level of clocks with the fabric logic (simple MUXes in RTL) and then to multiplex them with a BUFGCTRL.
Finally I used a BUFGCE to clock gate part of the logic. This reduces the number of BUFG per region to 2 (still not enough, but better than 4), the logic has no glitches on the output clock and the scheme looks like the following:
clk0 _
|_
_ RTL_MUX (LUT)___
clk1 _| |
|__
clk2 _ __BUFGCTRL____BUFGCE_______logic
|_ | |
_ RTL_MUX (LUT)____| |__clock_gating/selection_logic
clk3 _|
This attempt worked with a portion of the design and everything runs correctly. However when I instantiate the entire design (rougtly 50% occupation on the V2000), Vivado is unable to fix hold violations.
In addition, with both the full design and the smaller portion, I still warnings, which I don't know how to resolve. Maybe if I could fix those, I would have more chances to get a working design.
This is the warning I'm getting:
[Place 30-568] A LUT 'clkmux_3/bufgctrl_1_i_2' is driving clock pin of 24 registers. This could lead to large hold time violations. First few involved registers are:
I checked the schematic and the clocks multiplexed with the LUTs go straight to the BUFGCTRL, which is the one driving the registers listed in the warming. Does this mean that even if I use a BUFG, Vivado is still detecting that the clock originates from an LUT (the input to the BUFG)? Do you know a workaround?
Thank you in advance. Kind regards.
Paolo

Hi,
Ideally what you are trying to do is using gated clocks. Clock should in general not be gated through LUT's or fabric logic. You should use buffers to do that. However in your case, considering you have taken care of the hold violations and the timing, you can safely ignore these warnings. This warnings just warns you about the clock gating throught he LUT's which might affect the device timing. Write proper timing constraints and make sure you meet timing. That shoud do.

FIFO across clock domains

I'm using a FlexRIO 7966R for digital signal manipulation and need to buffer data across clock domains. By buffer I mean I need to be able to store in memory a variable amount of data before it's read back out in order to achieve a data delay. I can successfully write to the FIFO in one clock domain and read data from the FIFO in another clock domain, but as soon as I introduce the "Get Number of Elements to Read" function the compilation fails with a timing violation. It appears that this method cannot execute quickly enough:
I tried moving the "Get Number of Elements to Read" function into another slower clock domain SCTL but the compiler then states that it has to be in the same clock domain as the Read FIFO function, so that doesn't help.
Any thoughts anyone?
Thoric (CLA, CLED, CTD and LabVIEW Champion)

Intaris wrote:
Correct, BRAM does not cross clock domains. This is why i proposed splitting the work into two parts, domain crossing and delay.
Using the BRAM on the receivinG side only you can implement a circular buffer of size x with write index incremented each cycle and the read position is relative to this. By changing the offset between write and read (all on the receiver side) you can implement any delay up to x. Your receiver order would be read FIFO (in every cycle), write to BRAM, read from BRAM and continue.
That way your FIFO for crossing domains can be much smaller, saving LUTs and registers.
Regarding recucing the delay: If your sender is sending data as fast as your receiver can read them, reducing the delay sounds like it is always going to be lossy. You can do this with the BRAM by adjusting the offset between write and read accordingly, effectively skipping data.
Im in the mountains on holiday so i cant post code for another week.....
Other topic.... I though the max clock on a 7966 was 326 MHz? I know on a 7965 its listed as 326 MHz.
Thanks for the insight Intaris.
My FIFOs are set to use BRAM, so will your proposal of creating a small FIFO for crossing the clock domains plus a separate BRAM block for buffering achieve much saving in fabric? Isn't that the same amount of BRAM, plus a bit for your FIFO? I might go ahead and create a test implementation to see the difference in FPGA resource usage...
I'm using a 5782 Module with independent 500MHz clock.
Thoric (CLA, CLED, CTD and LabVIEW Champion)

LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)

Hello NI forums,
Question:
See the attached picture from a modified version of the LabVIEW DRAM FIFO example. It probably explains my question more effectively than the paragraphs below.
What is the difference to the LabVIEW / Xilinx compiliers, if any, between placing two independent branches of code in the same SCTL, versus placing them in individual SCTLs (in the same clock domain)?
Misc. comments:
I have briefly experimented with this concept using the included LabVIEW DRAM FIFO example (example finder >> Hardware Input and Output >> FlexRIO >> External Memory >> Simple External Memory FIFO.lvproj).
I compiled the default example (the read and write interfaces are in separate 40MHz SCTLs) five separate times. Then I put the read and write interfaces in the same 40MHz SCTL and compiled another five times. The result (when both read and write interfaces were in the same SCTL) was a reduction in resource usage (according to the compilation summary).
However, due to my lack of knowledge I'm hesitant to conclude that placing everything in one SCTL is always the best option. For example, I do not know what is created 'behind the scenes' with each SCTL. Perhaps putting independent branches of code in separate SCTLs makes it possible to route clock, reset, implicit enable, etc. signals more effectively.
Background information:
My task involves acquiring 2 channels of analog data using the NI 5772 and PXIe-7966. Data acquisition takes place in a 200MHz SCTL, and downstream processing is performed in a 100MHz SCTL.
During a vast majority of the 100MHz SCTL processing stages of the FPGA VI, the 2 channels of data do not interact with eachother. So it would be easy for me to place them in separate 100MHz loops if doing so would somehow help the design (timing, resource usage, etc.).
Thanks!
Attachments:
question.png ‏76 KB

Intaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
‎10-28-2014 12:11 PM
Just out of interest, what is the resource usage differential between the two versions?
In response to the above comment,
This is a little embarrassing, but it seems like the resource usage is similar than I initially thought for this particular example. I think the previous compilations that I based my assumption on coincidentally used more resources in the 2-SCTL loop case. I just compiled each version two additional times (see below).
Here's the version with everything in one loop:
Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Here's the version with the read and write in separate loops:
Device Utilization
Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4852 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 19.4% (2859 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4859 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)

How do i use my own domain name with creative cloud?

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http://forums.adobe.com/community/behance is where you would ask about publishing to "something else" from that program
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I hope we can work out a solution for this.
Met vriendelijke groet,
Peter Gerritsen
Engineer
AndoBurg BV
Voorstraat 31
3931 HB Woudenberg
T 033 479 40 80
F 033 479 40 89
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Als u niet de geadresseerde van dit bericht bent, verzoeken wij u ons hiervan op de hoogte te brengen en het bericht te verwijderen. AndoBurg BV aanvaardt geen aansprakelijkheid voor schade die voortvloeit uit elektronische verzending van informatie. Aan de inhoud van deze e-mail en eventuele bijlagen kunnen geen rechten worden ontleend, tenzij schriftelijk anders is overeengekomen.
Van: brogers_1
Verzonden: vrijdag 19 september 2014 20:10
Aan: Peter Gerritsen
Onderwerp: Can't open secured documents on windows 7 domain client with mandatory profiles.
Can't open secured documents on windows 7 domain client with mandatory profiles.
created by brogers_1<https://forums.adobe.com/people/brogers_1> in Enterprise Deployment (Acrobat and Reader) - View the full discussion<https://forums.adobe.com/message/6745441#6745441>

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Robert Pearman SBS MVP
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Clock Domain Crossing with FIFO

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