Clock instantiation - Counter in GTH IP Core

Question

Hi,
I am trying to intergrate GTH transceiver in my module. Here is the heirarchy.
TB --> Top --> IP core and Counter module.
I have a clock clk defined in the counter module. I instantiated the .veo file of the IP core and the counter module in the top module of my design. In the top module I pass the 80 bit dataout from the counter to the txdata_in in the IP core. I use the same clock clk, and at every posedge the outdata from the counter is passed to the txdata_in. I can see in the simulation the data being assigned.
Here is the question, I havent initialized most of the clock in the IP core and it shows x there. I cannot figure out what should be my reference clock which synchronizes both the modules(Counter and GTH IP core). I cannot understand how should I use the clocks of IP core. I went through the UG576 and UG472 but could not find how the clock can be integrated with my design. Which is the reference clock, how the freerun clock is to be used. Here is the code I am using:
Counter Module
`timescale 1ns / 1ps
//Counter
module counter    (
    out      ,  // Output of the counter
    clk     ,  // clock input
    reset       // reset input
    //----------Output Ports--------------
    output [79:0] out;
    //------------Input Ports--------------
    input clk, reset;
    //------------Internal Variables--------
    reg [79:0] out;
    //-------------Code Starts Here-------
    initial out = 0;
    always @(posedge clk)
    if (reset)
    begin // active high reset
        out <= 79'b0 ;
    end
    else
    begin
        out <= out + 1'b1;
    end
    endmodule
Top Module
`timescale 1ns / 1ps
//Counter Test Bench
module Counter_Top(clk,gtrefclk00_in,reset,out,gtwiz_userdata_rx_out,gtwiz_userdata_tx_in,gthrxn_in,gthrxp_in,rxusrclk_in,rxusrclk2_in,txusrclk_in,txusrclk2_in, gtwiz_userclk_tx_active_in,gtwiz_userclk_rx_active_in,gtwiz_reset_clk_freerun_in,gtwiz_reset_all_in,gtwiz_reset_tx_pll_and_datapath_in,gtwiz_reset_tx_datapath_in,gtwiz_reset_rx_pll_and_datapath_in,gtwiz_reset_rx_datapath_in,gtwiz_reset_rx_cdr_stable_out,gtwiz_reset_tx_done_out,gtwiz_reset_rx_done_out,qpll0outclk_out,txoutclk_out,txpmaresetdone_out,qpll0outrefclk_out,gthtxn_out,gthtxp_out,rxoutclk_out,rxpmaresetdone_out);
    // Declare inputs as regs and outputs as wires
    //Inputs
    input wire gtrefclk00_in,reset,clk;
    input wire gthrxn_in,gthrxp_in,rxusrclk_in,rxusrclk2_in,txusrclk_in,txusrclk2_in, gtwiz_userclk_tx_active_in,gtwiz_userclk_rx_active_in,gtwiz_reset_clk_freerun_in,gtwiz_reset_all_in,gtwiz_reset_tx_pll_and_datapath_in,gtwiz_reset_tx_datapath_in,gtwiz_reset_rx_pll_and_datapath_in,gtwiz_reset_rx_datapath_in;
    output reg [79:0] gtwiz_userdata_tx_in;
    //Ouputs
    output wire [79:0] out;
    output wire [79:0] gtwiz_userdata_rx_out;
    output wire gtwiz_reset_rx_cdr_stable_out,gtwiz_reset_tx_done_out,gtwiz_reset_rx_done_out,qpll0outclk_out,txoutclk_out,txpmaresetdone_out,qpll0outrefclk_out,gthtxn_out,gthtxp_out,rxoutclk_out,rxpmaresetdone_out;
always@(posedge clk)
    if (reset)
    begin // active high reset
        gtwiz_userdata_tx_in <= 79'b0 ;
    end
    else
    begin
        gtwiz_userdata_tx_in <= out;
    end
gtwizard_ultrascale_0 U2 (
  .gtwiz_userclk_tx_active_in(gtwiz_userclk_tx_active_in),                  // input wire [0 : 0] gtwiz_userclk_tx_active_in
  .gtwiz_userclk_rx_active_in(gtwiz_userclk_rx_active_in),                  // input wire [0 : 0] gtwiz_userclk_rx_active_in
  .gtwiz_reset_clk_freerun_in(gtwiz_reset_clk_freerun_in),                  // input wire [0 : 0] gtwiz_reset_clk_freerun_in
  .gtwiz_reset_all_in(gtwiz_reset_all_in),                                  // input wire [0 : 0] gtwiz_reset_all_in
  .gtwiz_reset_tx_pll_and_datapath_in(gtwiz_reset_tx_pll_and_datapath_in),  // input wire [0 : 0] gtwiz_reset_tx_pll_and_datapath_in
  .gtwiz_reset_tx_datapath_in(gtwiz_reset_tx_datapath_in),                  // input wire [0 : 0] gtwiz_reset_tx_datapath_in
  .gtwiz_reset_rx_pll_and_datapath_in(gtwiz_reset_rx_pll_and_datapath_in),  // input wire [0 : 0] gtwiz_reset_rx_pll_and_datapath_in
  .gtwiz_reset_rx_datapath_in(gtwiz_reset_rx_datapath_in),                  // input wire [0 : 0] gtwiz_reset_rx_datapath_in
  .gtwiz_reset_rx_cdr_stable_out(gtwiz_reset_rx_cdr_stable_out),            // output wire [0 : 0] gtwiz_reset_rx_cdr_stable_out
  .gtwiz_reset_tx_done_out(gtwiz_reset_tx_done_out),                        // output wire [0 : 0] gtwiz_reset_tx_done_out
  .gtwiz_reset_rx_done_out(gtwiz_reset_rx_done_out),                        // output wire [0 : 0] gtwiz_reset_rx_done_out
  .gtwiz_userdata_tx_in(gtwiz_userdata_tx_in),                              // input wire [79 : 0] gtwiz_userdata_tx_in
  .gtwiz_userdata_rx_out(gtwiz_userdata_rx_out),                            // output wire [79 : 0] gtwiz_userdata_rx_out
  .gtrefclk00_in(gtrefclk00_in),                                            // input wire [0 : 0] gtrefclk00_in
  .qpll0outclk_out(qpll0outclk_out),                                        // output wire [0 : 0] qpll0outclk_out
  .qpll0outrefclk_out(qpll0outrefclk_out),                                  // output wire [0 : 0] qpll0outrefclk_out
  .gthrxn_in(gthrxn_in),                                                    // input wire [0 : 0] gthrxn_in
  .gthrxp_in(gthrxp_in),                                                    // input wire [0 : 0] gthrxp_in
  .rxusrclk_in(rxusrclk_in),                                                // input wire [0 : 0] rxusrclk_in
  .rxusrclk2_in(rxusrclk2_in),                                              // input wire [0 : 0] rxusrclk2_in
  .txusrclk_in(txusrclk_in),                                                // input wire [0 : 0] txusrclk_in
  .txusrclk2_in(txusrclk2_in),                                              // input wire [0 : 0] txusrclk2_in
  .gthtxn_out(gthtxn_out),                                                  // output wire [0 : 0] gthtxn_out
  .gthtxp_out(gthtxp_out),                                                  // output wire [0 : 0] gthtxp_out
  .rxoutclk_out(rxoutclk_out),                                              // output wire [0 : 0] rxoutclk_out
  .rxpmaresetdone_out(rxpmaresetdone_out),                                  // output wire [0 : 0] rxpmaresetdone_out
  .txoutclk_out(txoutclk_out),                                              // output wire [0 : 0] txoutclk_out
  .txpmaresetdone_out(txpmaresetdone_out)                                  // output wire [0 : 0] txpmaresetdone_out
    // Connect DUT to test bench
    counter U1 (
    .clk(clk),
    .reset(reset),
    .out(out)
    endmodule
TB
`timescale 1ns / 1ps
// Company:
// Engineer:
// Create Date: 06/26/2015 05:01:59 PM
// Design Name:
// Module Name: Counter_Top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
// Dependencies:
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
module Counter_Tb();
reg clk,gtrefclk00_in,reset,gthrxn_in,gthrxp_in,rxusrclk_in,rxusrclk2_in,txusrclk_in,txusrclk2_in, gtwiz_userclk_tx_active_in,gtwiz_userclk_rx_active_in,gtwiz_reset_clk_freerun_in,gtwiz_reset_all_in,gtwiz_reset_tx_pll_and_datapath_in,gtwiz_reset_tx_datapath_in,gtwiz_reset_rx_pll_and_datapath_in,gtwiz_reset_rx_datapath_in;
wire [79:0] gtwiz_userdata_tx_in;
wire [79:0] out, gtwiz_userdata_rx_out;
wire gtwiz_reset_rx_cdr_stable_out,gtwiz_reset_tx_done_out,gtwiz_reset_rx_done_out,qpll0outclk_out,txoutclk_out,txpmaresetdone_out,qpll0outrefclk_out,gthtxn_out,gthtxp_out,rxoutclk_out,rxpmaresetdone_out;
// Initialize all variables
    initial
     begin     
        clk = 0;       // initial value of clock
        reset = 1;       // initial value of reset
        #5  reset = 0;    // Assert the reset
        #1000000000  $finish;      // Terminate simulation
    end
    // Clock generator
    always
    begin
        #5  clk = ~clk; // Toggle clock every 5 ticks
    end
Counter_Top U3(clk,gtrefclk00_in,reset,out,gtwiz_userdata_rx_out,gtwiz_userdata_tx_in,gthrxn_in,gthrxp_in,rxusrclk_in,rxusrclk2_in,txusrclk_in,txusrclk2_in, gtwiz_userclk_tx_active_in,gtwiz_userclk_rx_active_in,gtwiz_reset_clk_freerun_in,gtwiz_reset_all_in,gtwiz_reset_tx_pll_and_datapath_in,gtwiz_reset_tx_datapath_in,gtwiz_reset_rx_pll_and_datapath_in,gtwiz_reset_rx_datapath_in,gtwiz_reset_rx_cdr_stable_out,gtwiz_reset_tx_done_out,gtwiz_reset_rx_done_out,qpll0outclk_out,txoutclk_out,txpmaresetdone_out,qpll0outrefclk_out,gthtxn_out,gthtxp_out,rxoutclk_out,rxpmaresetdone_out);
endmodule
 

Answer 1

Hi
I suggest you to go through the Gt wizard example design which will give you all the details required of interfacing with the transceiver and clocking.
http://www.xilinx.com/support/documentation/ip_documentation/gtwizard/v3_3/pg168-gtwizard.pdf