"CMD_PATTERN= CGEN_PRBS" option doesn`t work properly in example design

Hi, 
I am using V6; MIG 3.6.1.
When I use the option above, CGEN_PRBS, the memory controller is trying to wirte and read to "bank x"
and Micron DDR3 memory model gave me the error, stopping simulation.
  parameter BEGIN_ADDRESS           = 32'h05fff300;
  parameter PRBS_SADDR_MASK_POS     = 32'h05fff300;
  parameter END_ADDRESS             = 32'h060003ff;
  parameter PRBS_EADDR_MASK_POS     = 32'hf9fffc00;
These are my boundary for addressing, and those works well when I use "CGEN_SEQUNTIAL"
Hence, I don`t think there may be problem, but I submitted for your information.
Thank you in advace for your answer.

Thank for reply, but seemed to be unclear about my problems.
I have changed the option, "CGEN_ALL" in sim_tb_top.v which is top test-bench.
And, the option, "modify_enable_sel" in example_top is assigned to "1" by default, and it is used when I want to the various configuration with vio_data_*, vio_addr_* combinations.
My problem isn`t about custom setting of addr/cmd/data.
I`m tryingn to use a given example code & test-bench, and its option(of sim_tb_top.v)
I`ve attached my console messages right after "calibration done"
libration Done
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 65925100.0 ps INFO: Refresh  
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66035100.0 ps INFO: Activate  bank 0 row 0000
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66045100.0 ps INFO: Activate  bank x row xxxx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66055100.0 ps INFO: Activate  bank x row xxxx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66057600.0 ps INFO: Read      bank 0 col 000, auto precharge 0
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66065100.0 ps INFO: Activate  bank x row xxxx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66076350.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ff
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66077600.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 00
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66078850.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = aa
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66080100.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 55
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66081350.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 55
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66082600.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = aa
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66083850.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 99
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66085100.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 66
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.main: at time 66110100.0 ps INFO: Sync On Die Termination Rtt_NOM =         60 Ohm
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66112600.0 ps INFO: Write     bank x col xxX, auto precharge 0
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66122600.0 ps INFO: Write     bank x col xxX, auto precharge 0
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66128850.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66130100.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66131350.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66132600.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66132600.0 ps INFO: Write     bank x col xxX, auto precharge 0
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66133850.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66135100.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66136350.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66137600.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
libration Donesim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 65925100.0 ps INFO: Refresh  sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66035100.0 ps INFO: Activate  bank 0 row 0000sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66045100.0 ps INFO: Activate  bank x row xxxxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66055100.0 ps INFO: Activate  bank x row xxxxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66057600.0 ps INFO: Read      bank 0 col 000, auto precharge 0sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66065100.0 ps INFO: Activate  bank x row xxxxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66076350.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000000 data = ffsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66077600.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000001 data = 00sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66078850.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000002 data = aasim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66080100.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000003 data = 55sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66081350.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000004 data = 55sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66082600.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000005 data = aasim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66083850.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000006 data = 99sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66085100.0 ps INFO: READ @ DQS= bank = 0 row = 0000 col = 00000007 data = 66sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.main: at time 66110100.0 ps INFO: Sync On Die Termination Rtt_NOM =         60 Ohmsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66112600.0 ps INFO: Write     bank x col xxX, auto precharge 0sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66122600.0 ps INFO: Write     bank x col xxX, auto precharge 0sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66128850.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66130100.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66131350.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66132600.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.cmd_task: at time 66132600.0 ps INFO: Write     bank x col xxX, auto precharge 0sim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66133850.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66135100.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66136350.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xxsim_tb_top.comp_inst.mem_rnk[0].mem_8_4.gen_mem[0].u_comp_ddr3.data_task: at time 66137600.0 ps INFO: WRITE @ DQS= bank = x row = xxxx col = xxxxxxxx data = xx
The options I used are mentioned my first questions, and nothing is changed.
I`ve tested option "CGEN_SEQUNETIAL" and full range of my setting address, and in that case, there is no problem.
I think, therefore, BEGIN/END address are not the cause of problem.
For your information,
I used DDR3 model of Micron, which Xilinx ISE provide in defalut.
I really want to use the option CGEN_PRBS... :)
Help me out
 

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