Connect MMCM with differentia input to differential clock on VC707

Question

Hi All,
I am trying to connect my design ( 40 MHz ) to the MMCM after connecting MMCM input to the 200 MHz LVDS differential clock (on E18, E19 of VC707). I am using constraints from the Master Constraints File Listing:-
set_property PACKAGE_PIN E19 [get_ports clk_in_p]
set_property PACKAGE_PIN E18 [get_ports clk_in_n]
set_property IOSTANDARD LVDS [get_ports clk_in_p]
set_property IOSTANDARD LVDS [get_ports clk_in_n]
The top level module (PO_Estimation_Subsystem.vhd) has (clk_in_p, clk_in_n) which are connected to the MMCM and also the external pins (E18, E19) and the output clock from the MMCM is later connected to my design.
From the clock wizard GUI and also from the output files (clk_wiz_0.vhd, clk_wiz_0_clk_wiz.vhd), it is clear that the required buffers are already instantiated, but you can double check it.
I currently have the following errors:-
[DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port clk_in_p is Single-Ended but has an IOStandard of LVDS which can only support Differential
[DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port clk_in_n is Single-Ended but has an IOStandard of LVDS which can only support Differential
* I read similar posts to differential clocks and related application notes, but I still can't figure out what is the problem here:-
http://www.xilinx.com/support/answers/57109.html 
http://www.xilinx.com/support/answers/38656.html

Answer 1

Hello ,
The problem is in PO_Estimation_Subsystem.vhd file. You should declare output port for this module in order to successfully implement your design. As an example, your entity should look like 
ENTITY PO_Estimation_Subsystem IS
PORT (clk_in_p : IN std_logic;
clk_in_n : IN std_logic;
clk_out : out std_logic
END PO_Estimation_Subsystem;
One more problem is in the port names of instantiation of clk_wiz_0 in top level module. You need to replace it with -
component clk_wiz_0
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
end component;
Do the necessary modifications in port-mapping names as well. I am attaching modified file for your reference.
Note : You must declare the output in the entity in order to place the design successfully.