Scope differential clock
Hello,
I am working with Vivado 2015.1 and a ZC706 board. I want to scope the differential clock that comes as input to pins W8 (SMA_MGT_REFCLK_P) and W7 (SMA_MGT_REFCLK_N).
I have contstrained the pins as follows in the xdc file:
set_property PACKAGE_PIN W8 [get_ports {mgt_ref_clk_clk_p}]
set_property PACKAGE_PIN W7 [get_ports {mgt_ref_clk_clk_n}]
create_clock -period 6.400 -name TS_MGT_REF_CLK [get_ports {mgt_ref_clk_clk_p}]
In order to scope the clock, I have added a 1-bit counter to the block diagram that will be clocked by the mgt_ref_clk. This is a part of my block design in Vivado:
The "mgt_ref_clk" is an "interface port" of type "xilinx.com:interface:diff_clock_rtl:1.0":
My problem is that I can not understand how to connect the "mgt_ref_clk" port to the utility buffer in order to create a single-ended clock that will be connected to the counter.
EDIT1: I tried the following connections (create simple input ports as clock signals):
However Vivado reports the following error:
[Vivado 12-1411] Cannot set LOC property of ports, Illegal to place instance base_zynq_design_i/util_ds_buf_2/U0/USE_IBUFDS.GEN_IBUFDS[0].IBUFDS_I on site W8. The location site type does not match the instance type. ["C:/Work/AXIOM/WorkingDirectory/axi_dma_fifo/project_1.srcs/constrs_1/new/base_zynq_design_wrapper.xdc":15]
What does it mean "The location site type does not match the instance type"?
Thanks,
Dimitris
Hello Austin,
Thanks for your reply. Since I am using the Aurora core, I will try to debug it.
In the Aurora v10.0 manual (page 74, chapter 4), I saw that there is an option called "Vivado lab tools":
However, when I try to configure my Aurora core, I get this window that is missing this option (!):
I tried to scroll down, mark other options in case it appears, but nothing. Do you know if this is a bug or am I missing something?
Thanks,
Dimitris
Similar Messages
-
Connect MMCM with differentia input to differential clock on VC707
Hi All,
I am trying to connect my design ( 40 MHz ) to the MMCM after connecting MMCM input to the 200 MHz LVDS differential clock (on E18, E19 of VC707). I am using constraints from the Master Constraints File Listing:-
set_property PACKAGE_PIN E19 [get_ports clk_in_p]
set_property PACKAGE_PIN E18 [get_ports clk_in_n]
set_property IOSTANDARD LVDS [get_ports clk_in_p]
set_property IOSTANDARD LVDS [get_ports clk_in_n]
The top level module (PO_Estimation_Subsystem.vhd) has (clk_in_p, clk_in_n) which are connected to the MMCM and also the external pins (E18, E19) and the output clock from the MMCM is later connected to my design.
From the clock wizard GUI and also from the output files (clk_wiz_0.vhd, clk_wiz_0_clk_wiz.vhd), it is clear that the required buffers are already instantiated, but you can double check it.
I currently have the following errors:-
[DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port clk_in_p is Single-Ended but has an IOStandard of LVDS which can only support Differential
[DRC 23-20] Rule violation (IOSTDTYPE-1) IOStandard Type - I/O port clk_in_n is Single-Ended but has an IOStandard of LVDS which can only support Differential
* I read similar posts to differential clocks and related application notes, but I still can't figure out what is the problem here:-
http://www.xilinx.com/support/answers/57109.html
http://www.xilinx.com/support/answers/38656.htmlHello ,
The problem is in PO_Estimation_Subsystem.vhd file. You should declare output port for this module in order to successfully implement your design. As an example, your entity should look like
ENTITY PO_Estimation_Subsystem IS
PORT (clk_in_p : IN std_logic;
clk_in_n : IN std_logic;
clk_out : out std_logic
END PO_Estimation_Subsystem;
One more problem is in the port names of instantiation of clk_wiz_0 in top level module. You need to replace it with -
component clk_wiz_0
port
(-- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_out1 : out std_logic;
-- Status and control signals
reset : in std_logic;
locked : out std_logic
end component;
Do the necessary modifications in port-mapping names as well. I am attaching modified file for your reference.
Note : You must declare the output in the entity in order to place the design successfully.
-
Need help to interface InRevium's TB-FMCH-HDMI4K Board with ZC706 Eval board
We (PathPartner Technology Consulting Services) have recently procured the above-mentioned card(from Inrevium) for supporting HDMI display (HDMI2.0 for 4K) for our FPGA-based Video Codec solution.
We are implementing this solution on ZC706 board (Zynq-7045 based)
We did get access to reference designs from Xilinx’s HDMI Reference Design lounge wherein the Reference design is targeted for KC705 evaluation board. It seemed feasible to implement the same design on ZC706 board since both the devices in KC705 and ZC706 use the same XCVR.
While implementing the design on ZC706 board, we could not generate bitfiles due to DRC violations. We did set the pin assignments made in XDC file targetting ZC706 (compared to KC705).
The DRC errors are:
[DRC 23-20] Rule violation (RTSTAT-2) Partially routed net - 1 net(s) are partially routed. The problem bus(es) and/or net(s) are IPI_INST/hdmi_ipi_i/hdmi_gt_0/inst/drurefclk_to_qpll.
[DRC 23-20] Rule violation (UCIO-1) Unconstrained Logical Port - 2 out of 49 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: DRU_CLK_P_IN, DRU_CLK_N_IN.
[Vivado 12-1345] Error(s) found during DRC. Bitgen not run.
Delving further:
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN]
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation on ZC706 board (we have retained the file name similar to one used for KC705 in the reference design).
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN. Need to know how RX can be disabled.
Looking forward for guidance in resolving the above-mentioned...
Thanks and Regards
Lalith
Hi Satish,
For the TB-FMCH-HDMI4K Card that we have procured from InRevium, we have got a reference design that is targetted for KC705 board. We have a ZC706 board and intend to get this card operational on ZC706. It seemed feasible since both the devices in KC705 and ZC706 use the same XCVR.
The HDMI 2.0 Design requires GT differential clock pairs for 3 of its clocks, the pins are as mentioned below:
In the reference design that is based on the KC705 board, these pins are connected to the approriate GT Differential clock pairs as below:
set_property PACKAGE_PIN C8 [get_ports HDMI_RX_CLK_P_IN] (FMC_HPC_GBTCLK0_M2C_P on KC705)
set_property PACKAGE_PIN G8[get_ports DRU_CLK_P_IN] (SMA_MGT_REFCLK_P on KC705)
set_property PACKAGE_PIN E8 [get_ports TX_REFCLK_P_IN] (FMC_HPC_GBTCLK1_M2C_P on KC705)
But in case of ZC706 we could find only 2 GT pairs: FMC_HPC_GBTCLK0_M2C and FMC_HPC_GBTCLK1_M2C that corresponds to pins AD10 and AA8 respectively.
We could not find another differential clock pin on HPC connector with similar properties for DRU_CLK_P_IN.
We have set the constraints as follows:
set_property PACKAGE_PIN AD10 [get_ports HDMI_RX_CLK_P_IN]
set_property PACKAGE_PIN AA8 [get_ports TX_REFCLK_P_IN]
and
set_property PACKAGE_PIN AF10 [get_ports DRU_CLK_P_IN]: Need to find an appropriate pin on ZC706 board
Please refer to the attached .xdc file that we are using for the bit file generation.
It will help us if we can find an alternative pin for the DRU_CLK_P_IN on ZCZ706 board
Another alternative would be: We do not need the RX port. Hence, if RX can be completely disabled, the RX CLK pin can be used for DRU_CLK_P_IN. Need to know how RX can be disabled.
Looking forward for your guidance in resolving the same
Thanks and Regards
Lalith
-
Hey all, me and my work partner have a question since when we import the part PLCC-28 (This is just a differential clock driver) the part itself has DRC erros even though
is from the NI library!
Design Rule Error: Net VCC Close To Net 0
Design Rule Error: Net SMA20 Close To Unused Pin.
This is because the top right pin and right pin on top seem to be too close to each other....is there anyway this can be a mistake in the original package file...also I tried right clicking the
part and doing an in place part edit and I managed to move the pins a bit apart and then after I was done it showed no DRC errors...but the problem is you can move the pins around just like that right?
Any help would be great, let me know your thoughts on this.Hi, Design Rules Check (DRC) errors are defined by the designer, not by NI. You start with a default global setting that may or may not be good for your design. One of the first steps when you transfer a design is to actually define your design rules along with many other things.
If two pins are too close together, and you are getting a DRC, go to View > Clearances and you will see that most likely the clearance area around those two nets are too close together, you might need to select the specific pin, right-click and select properties, then on the Pin Properties dialog select the General tab, look for the Clearance field and decrease it. Or use the Spreadsheet View to locate those pins (SMT Pads tab or THT Pads tab), then use the Trace Clearance column to decrease it.
DO NOT move the pins away, usually footprints are designed to match the actual part when placed, if you move the pins you might not be able to fit the part once you place it to solder it.
Nestor
National Instruments -
Does kintex7 support LVPECL in HR bank
Hi,
For K7 FPGA (XC7K160T-2FFG676I), if the clock source of its differential clk input is 3.3V LVPECL , how to set the differential IO standards for FPGA and terminate it (IO in HR banks) ?
From UG471 “ 7 Series FPGAs SelectIO Resources User Guide”, can’t find LVPECL is supported by K7 FPGA. And our board without 2.5V power rails, it seems that 1.8V LVDS IO standard can be a candidate.
Can we just using the AC-Coupled and DC-Biased as attached picture "Termation for K7 differential clock input. jpg"? And VCCO is 1.8V. BTW, differential input is in HR banks.
Or is there any other IO standards and termination can be used for 3.3V LVPECL input?
Thanks!
The AC coupling showed in your post is one non-standard method for interfacing. Select the R-Bias and VCCO values in such a way that matching with receive side common mode voltage.
BTW where you are using that clock? Please note that in case if you are using that clock for reference clock of MGT kind of critical interfaces then you need to match with data sheet specifications in all aspects. -
[VIA] KT3 Ultra2 - - need to "Assign IRQ to VGA" in Bios but how?
G'day people,
I am having a little drama with the instalation of a new video card. The system recoginses a hardware device, and nVidia WDM Video Capture (Universal) bbut after driver install, I get an error This device cannot start (Code 10). The FAQ over at nVidia says that:
The Code 10 error is most often a result of not having the option "Assign IRQ to VGA" enabled in your motherboards system BIOS.
My problem is I cannot find how to enable this option in bios. Any ideas? Just going to reboot and edit this post with the BIOS version.
Okay.....When I enter Bios the info say AMIBIOS vers 3.31a.
Thanks.Thanks for this help people, I am quite new at this. Only been tinkering for about 5 years.
Quote
That's not the right number, I belive what you are looking at is the American Megatrend version, not the actual BIOS string. It's usually at the bottom of the screen.
The only available BIOS versions are 1.X or 5.X depending on the version of mobo you are using. You need to confirm that first.
Okay how about version 5.5 date is 07/10/02.
Quote
In which slot is the sound card?
Is there a modem involved somewhere?
Did you uninstall the previous card's driver properly? Enter SafeMode to find out.
Okay the sound card is in IRQ17 which it shares with an modem. (???)
Yes I made sure I uninstalled the old graphics card driver before I installed the new one.
Also:
Resource Share Device Description
IRQ 16 Shared Realtek RTL8139 Family PCI Fast Ethernet NIC #2
Resource Share Device Description
IRQ 16 Shared NVIDIA GeForce 6600
Could this be my problem???
Quote
What system are you running in your PC ? Did you enabled APIC Function in Advanced Bios Features ? You have said very few about your PC. so better explain with more detail your hardware ( Memory speed, system etc.)
System?? as in operating system? Win XP Pro. that is is my sig. will check on that APIC.
Extra info.
Field Value
Motherboard Properties
Motherboard ID 62-0710-009999-00101111-040201-VIA_K7$1AARK204_A6380VMS V5.5 071002
Motherboard Name MSI KT3 Ultra2 (MS-6380E)
Front Side Bus Properties
Bus Type DEC Alpha EV6
Bus Width 64-bit
Real Clock 133 MHz (DDR)
Effective Clock 267 MHz
Bandwidth 2133 MB/s
Memory Bus Properties
Bus Type DDR SDRAM
Bus Width 64-bit
Real Clock 167 MHz (DDR)
Effective Clock 333 MHz
Bandwidth 2666 MB/s
Chipset Bus Properties
Bus Type VIA V-Link
Bus Width 8-bit
Real Clock 67 MHz (QDR)
Effective Clock 267 MHz
Bandwidth 267 MB/s
Motherboard Physical Info
CPU Sockets/Slots 1
Expansion Slots 5 PCI, 1 AGP, 1 CNR
RAM Slots 3 DIMM
Integrated Devices Audio
Form Factor ATX
Motherboard Size 230 mm x 300 mm
Motherboard Chipset KT333
Extra Features Fuzzy Logic 4
Motherboard Manufacturer
Company Name Micro-Star International
Product Information http://www.msi.com.tw/program/products/mainboard/mbd/pro_mbd_list.php
BIOS Download http://www.msi.com.tw/program/support/bios/bos/spt_bos_list.php
And memory:
DIMM1
Field Value
Memory Module Properties
Module Name Kingmax MPMB62D-68KX3-MBA
Serial Number None
Module Size 256 MB (2 rows, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC2700 (166 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Normal (15.625 us), Self-Refresh
Memory Timings
@ 166 MHz 2.5-3-3-7 (CL-RCD-RP-RAS)
@ 133 MHz 2.0-3-3-6 (CL-RCD-RP-RAS)
Memory Module Features
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
Memory Module Manufacturer
Company Name Kingmax Inc.
Product Information http://www.kingmax.com/product/pro_newp.htm
DIMM 2
Field Value
Memory Module Properties
Serial Number None
Module Size 256 MB (1 rows, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC2700 (166 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Reduced (7.8 us), Self-Refresh
Memory Timings
@ 166 MHz 2.5-3-3-7 (CL-RCD-RP-RAS)
@ 133 MHz 2.0-3-3-6 (CL-RCD-RP-RAS)
Memory Module Features
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
AND DIMM 3
( I realize there is a mismatch here but have had no dramas as yet because of it, will try re-installing the hardware wit h this module removed)
Field Value
Memory Module Properties
Module Name Nanya M2U51264DS8HC3G-5T
Serial Number 884B2815h
Manufacture Date Week 48 / 2005
Module Size 512 MB (2 rows, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC3200 (200 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Reduced (7.8 us), Self-Refresh
Memory Timings
@ 200 MHz 3.0-3-3-8 (CL-RCD-RP-RAS)
@ 166 MHz 2.5-3-3-7 (CL-RCD-RP-RAS)
Memory Module Features
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
Memory Module Manufacturer
Company Name Nanya Technology Corp.
Product Information http://www.nanya.com/e-htm/abc/abc-03.htm
Thankyou for your help with this folks, really appreciate it and am having some fun learning. -
Hi,
I have been running an Athlon XP-M Barton Core at 2133mhz successfully for about 6+months and tonight it refuses to get past the screen that reads: Press Shift-Tab to try network boot, Try other boot devices......
After i clear the CMOS settings it will run but when i attempt a restart, it hangs up. Short of throwing out the board and using a Mercury KT600 as a replacement, this is my last hope.
MSI KT4A-V
FSB 133mhz
AMD Athlon XP-M 2800 2133mhz stable
1024 PC2700 DDR Ram
XFX 6800GT
Maxtor 200 DiamondMax 8Meg buffer
Cooler Master Aero CPU fan
Atrix 550 watt PSU
Any help please would be appreciatedIn very late reply to your help, it turned out to be a mainboard failure. Now I have the question of how to overclock the processor to 166 FSB. Here is my current config via Everest:
CPU Properties:
CPU Type Mobile AMD Athlon XP 3000+
CPU Alias Barton
CPU Stepping A2
CPUID CPU Name mobile AMD Athlon(tm) XP-M 2800+
CPUID Revision 000006A0h
CPU Speed:
CPU Clock 2159.56 MHz
CPU Multiplier 16.0x
CPU FSB 134.97 MHz
Memory Bus 168.72 MHz
CPU Cache:
L1 Code Cache 64 KB
L1 Data Cache 64 KB
L2 Cache 512 KB (On-Die, Full-Speed)
Motherboard Properties:
Motherboard ID 62-0909-009999-00101111-040201-VIA_K7$KT600300_A7021VMS V3.2 090904
Motherboard Name MSI KT6-V (MS-7021 v2.0) (5 PCI, 1 AGP, 2 DDR DIMM, Audio, LAN)
Chipset Properties:
Motherboard Chipset VIA VT8377 Apollo KT600
Memory Timings 2.5-3-3-7 (CL-RCD-RP-RAS)
Command Rate (CR) 2T
SPD Memory Modules:
DIMM1 1 GB PC3200 DDR SDRAM (3.0-3-3-8 @ 200 MHz) (2.5-3-3-7 @ 166 MHz) (2.0-2-2-6 @ 133 MHz)
DIMM2 1 GB PC3200 DDR SDRAM (3.0-3-3-8 @ 200 MHz) (2.5-3-3-7 @ 166 MHz) (2.0-2-2-6 @ 133 MHz)
BIOS Properties:
System BIOS Date 09/09/04
Video BIOS Date 04/29/06
DMI BIOS Version Version 07.00T
--------[ SPD ]---------------------------------------------------------------------------------------------------------
[ DIMM1: 1 GB PC3200 DDR SDRAM ]
Memory Module Properties:
Serial Number None
Module Size 1024 MB (1 rank, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC3200 (200 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Reduced (7.8 us), Self-Refresh
Memory Timings:
@ 200 MHz 3.0-3-3-8 (CL-RCD-RP-RAS)
@ 166 MHz 2.5-3-3-7 (CL-RCD-RP-RAS)
@ 133 MHz 2.0-2-2-6 (CL-RCD-RP-RAS)
Memory Module Features:
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
[ DIMM2: 1 GB PC3200 DDR SDRAM ]
Memory Module Properties:
Serial Number None
Module Size 1024 MB (1 rank, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC3200 (200 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Reduced (7.8 us), Self-Refresh
Memory Timings:
@ 200 MHz 3.0-3-3-8 (CL-RCD-RP-RAS)
@ 166 MHz 2.5-3-3-7 (CL-RCD-RP-RAS)
@ 133 MHz 2.0-2-2-6 (CL-RCD-RP-RAS)
Memory Module Features:
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
I try knocking down the multiplier to 12 and setting the FSB to 166 but the computer will not start and i have to clear CMOS to start over again. Any help at all would greatly be appreciated. -
No videosignal after putting 200 FSB
I wanted to o/c my athlon xp 2600+ to 11.5x200. But when i did save and exited bios everything booted even my gpu... i heard the fan starting to spin
but no videosignal ... i mean my screen keeps standing on standby so i was like hmmm maybe its the psu so i toke off the fan my hdd/dvd/cd still no signal so is it the RAM or ? ram info below... right out of aida32
Module Name Kingston K
Serial Number 702C2100h
Module Size 512 MB (2 rows, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC3200 (200 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Reduced (7.8 us), Self-Refresh
Highest CAS Latency 3.0 (5.0 ns @ 200 MHz)
2nd Highest CAS Latency 2.5 (6.0 ns @ 166 MHz)
Memory Module Features
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported^_^ hehe well lets say if you give me the €100+ ill get an enermax
not really a big choice to pay €100 and get 350 W
btw temps r 51C after playing battlefield 1942 for a h or 2-3 40C-45C when idle surfing listing music that kind of stuff -
AXI Ethernet Subsystem - PHY out of reset
Hi all,
I have been trying to use the AXI Ethernet Subsystem in the Mini ITX board (xc7z100ffg900-2) but I fail to take the internal PHY out of reset.
The Ethernet Subsystem is connected to a FIFO which is responsible for the block reset. I'm running the FIFO Interrupt Example that comes with the IP driver. The code gets stuck when checking for the MgtRdy bit. This seems to be because the on-chip PHY is not out of reset, since the PhyRstCmplt bit is also low.
The MGT_CLK interface is connected to the board VCO which is set up to generate a 125 MHz differential clock. The block is also connected to the board SFP.
In previous designs when I did not have a PHY (loopback setup using the MII/GMII interface) the core would work fine. This problem only came up when I instantiate the on-chip PHY. I tried using Vivado 2014.2 (1000BASE-X PCS/PMA) and Vivado 2015.1 (1G/2.5G Ethernet PCS/PMA) and no success in both cases.
Have anyone had a similar issue?
Is there any way to check if the VCO output is correct?
Thanks
Update: Phy is out of reset now but MgtRdy is still low. ISR reads 0x140.
What could be the reasons MgtRdy does not go high? -
845e ht ready and pc 2100 200/266 mhz 256 mb memmory module(s)
Hi all i am experiencing this problem on all my mainboards as described in the title, here it is:
Bios recognizes only 128 Mb of Ram no matter if they are 1 or 2 (same kind of modules), i tried BIOS update too.
The weird thing it's that it's happening on all my mainboards of this kind but when i'm trying the same memory modules on MSI VIA chipset based mainboards it all works fine.
Thank you in advance for your repliesmotherboard is MS-65663 ver 2
Here is the report generated by AIDA, i cutted off the stuff about the OS because it is too long if you need it i will post it in the reply if asked:
--------[ AIDA32 (c) 1995-2004 Tamas Miklos ]---------------------------------------------------------------------------
Version AIDA32 v3.93
Author [email protected]
Homepage http://www.aida32.hu
Report Type Report Wizard
Computer MARIUS
Generator M
Operating System Microsoft Windows XP Professional 5.1.2600 (WinXP Retail)
Date 2004-03-18
Time 01:06
--------[ Summary ]-----------------------------------------------------------------------------------------------------
Computer:
Operating System Microsoft Windows XP Professional
OS Service Pack None
Internet Explorer 6.0.2600.0000 (IE 6.0 - Windows XP)
Computer Name MARIUS
User Name M
Logon Domain MARIUS
Motherboard:
CPU Type Intel Celeron 4A, 2400 MHz (6 x 400)
Motherboard Name MSI 845E Max (MS-6566E) (6 PCI, 1 AGP, 1 CNR, 2 DIMM)
Motherboard Chipset Intel Brookdale i845E
System Memory 128 MB (PC2100 DDR SDRAM)
BIOS Type AMI (09/01/03)
Communication Port Communications Port (COM1)
Communication Port Communications Port (COM2)
Communication Port ECP Printer Port (LPT1)
Display:
Video Adapter Inno3D GeForce4 MX 440 with AGP8X (64 MB)
3D Accelerator nVIDIA GeForce4 MX 440 with AGP8X
Multimedia:
Audio Adapter Intel 82801DB(M) ICH4(-M) - AC'97 Audio Controller [B-0]
Storage:
Floppy Drive Floppy disk drive
Disk Drive SAMSUNG SP0401N
Optical Drive SONY CD-RW CRX230E
Partitions:
C: (FAT32) 4994 MB (3712 MB free)
D: (FAT32) 33188 MB (10932 MB free)
Input:
Keyboard Standard 101/102-Key or Microsoft Natural PS/2 Keyboard
Mouse PS/2 Compatible Mouse
Network:
Primary IP Address 217.10.212.188
Primary MAC Address 00-10-4B-6A-16-1D
Network Adapter 3Com EtherLink XL 10/100 PCI TX NIC (3C905B-TX) (217.10.212.188)
--------[ DMI ]---------------------------------------------------------------------------------------------------------
[ BIOS ]
BIOS Properties:
Vendor American Megatrends Inc.
Version 07.00T
Release Date 04/02/01
Size 512 KB
Boot Devices Floppy Disk, Hard Disk, CD-ROM, ATAPI ZIP, LS-120
Capabilities Flash BIOS, Shadow BIOS, Selectable Boot, EDD, BBS
Supported Standards DMI, APM, ACPI, ESCD, PnP
Expansion Capabilities ISA, PCI, AGP, USB
[ System ]
System Properties:
Manufacturer Micro-Star Inc.
Product MS-6566E
Version 1.0
Serial Number 00000000
Wake-Up Type Modem Ring
[ Motherboard ]
Motherboard Properties:
Manufacturer Micro-Star Inc.
Product MS-6566E
Version 1.0
Serial Number 00000000
[ Chassis ]
Chassis Properties:
Manufacturer Uknown Chassis Manufacture
Version Version 1.00
Serial Number 123456890
Asset Tag 0123ABC
Chassis Type Desktop Case
[ Memory Controller ]
Memory Controller Properties:
Error Detection Method None
Supported Memory Interleave 1-Way
Current Memory Interleave 1-Way
Supported Memory Types DIMM, SDRAM
Supported Memory Voltages 3.3V
Maximum Memory Module Size 1024 MB
Memory Slots 2
[ Processors / Intel(R) Pentium(R) 4 Processor ]
Processor Properties:
Manufacturer Intel
Version Intel(R) Pentium(R) 4 Processor
External Clock 100 MHz
Maximum Clock 3000 MHz
Current Clock 2400 MHz
Type Central Processor
Voltage 3.3 V, 2.9 V
Status Enabled
Socket Designation FC-478
[ Caches / Internal Cache ]
Cache Properties:
Type Internal
Speed 40 ns
Status Enabled
Operational Mode Write-Back
Associativity 4-way Set-Associative
Maximum Size 1024 KB
Installed Size 8 KB
Supported SRAM Type Synchronous
Current SRAM Type Synchronous, Pipeline Burst
Error Correction Single-bit ECC
Socket Designation Internal Cache
[ Caches / Internal Cache ]
Cache Properties:
Type Internal
Speed 40 ns
Status Enabled
Operational Mode Write-Back
Maximum Size 1024 KB
Installed Size 128 KB
Supported SRAM Type Synchronous
Current SRAM Type Synchronous
Error Correction Parity
Socket Designation Internal Cache
[ Memory Modules / DIMM1 ]
Memory Module Properties:
Socket Designation DIMM1
Type DIMM, SDRAM
Installed Size 512 MB
Enabled Size 512 MB
[ Memory Modules / DIMM2 ]
Memory Module Properties:
Socket Designation DIMM2
Installed Size Not Installed
Enabled Size Not Installed
[ System Slots / PCI1 ]
System Slot Properties:
Slot Designation PCI1
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ System Slots / PCI2 ]
System Slot Properties:
Slot Designation PCI2
Type PCI
Usage In Use
Data Bus Width 32-bit
Length Long
[ System Slots / PCI3 ]
System Slot Properties:
Slot Designation PCI3
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ System Slots / PCI4 ]
System Slot Properties:
Slot Designation PCI4
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ System Slots / PCI5 ]
System Slot Properties:
Slot Designation PCI5
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ System Slots / PCI6 ]
System Slot Properties:
Slot Designation PCI6
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ System Slots / AGP ]
System Slot Properties:
Slot Designation AGP
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ System Slots / CNR ]
System Slot Properties:
Slot Designation CNR
Type PCI
Usage Empty
Data Bus Width 32-bit
Length Long
[ Port Connectors / Def ]
Port Connector Properties:
Port Type SSA SCSI
Internal Reference Designator USB
Internal Connector Type Mini-Centronics
External Reference Designator Def
External Connector Type DB-25 pin male
--------[ Sensor ]------------------------------------------------------------------------------------------------------
Sensor Properties:
Sensor Type Winbond W83627HF
Sensor Access ISA 290h
Temperatures:
Motherboard 24 °C (75 °F)
CPU 20 °C (68 °F)
Cooling Fans:
CPU 2596 RPM
Voltage Values:
CPU Core 1.49 V
CPU Aux 1.82 V
+3.3 V 3.26 V
+5 V 5.19 V
+12 V 11.98 V
-12 V -12.36 V
-5 V -5.25 V
+5 V Standby 5.04 V
VBAT Battery 3.09 V
Debug Info 5D 72 CC C1 C5 1F 31 18 FF FF 41 64 (01)
--------[ CPU ]---------------------------------------------------------------------------------------------------------
CPU Properties:
CPU Type Intel Celeron 4A, 2400 MHz (6 x 400)
CPU Alias Northwood-128
CPU Stepping D1
Original Clock 2400 MHz
L1 Trace Cache 12K Instructions
L1 Data Cache 8 KB
L2 Cache 128 KB (On-Die, ATC, Full-Speed)
CPU Physical Info:
Package Type 478 Pin uPGA
Package Size 3.50 cm x 3.50 cm
Transistors 55 million
Process Technology 6M, 0.13 um, CMOS, Cu, Low-K
Die Size 131 mm2
Core Voltage 1.475 - 1.55 V
I/O Voltage 1.475 - 1.55 V
Typical Power 38.7 - 82 W (depending on clock speed)
Maximum Power 49 - 103 W (depending on clock speed)
CPU Manufacturer:
Company Name Intel Corporation
Product Information http://www.intel.com/products/browse/processor.htm
CPU Utilization:
CPU #1 100 %
--------[ CPUID ]-------------------------------------------------------------------------------------------------------
CPUID Properties:
CPUID Manufacturer GenuineIntel
CPUID CPU Name Intel(R) Celeron(R) CPU 2.40GHz
CPUID Revision 0F29h
IA Brand ID 0Ah (Intel Celeron 4)
Platform ID 0Fh (Socket 478)
IA CPU Serial Number Unknown
Instruction Set:
AMD 3DNow! Not Supported
AMD 3DNow! Professional Not Supported
AMD Enhanced 3DNow! Not Supported
AMD Extended MMX Not Supported
AMD64 Not Supported
Cyrix Extended MMX Not Supported
IA-64 Not Supported
IA MMX Supported
IA SSE Supported
IA SSE 2 Supported
IA SSE 3 Not Supported
CLFLUSH Instruction Supported
CMPXCHG8B Instruction Supported
CMPXCHG16B Instruction Not Supported
Conditional Move Instruction Supported
FEMMS Instruction Not Supported
MONITOR / MWAIT Instruction Not Supported
CPUID Features:
36-bit Page Size Extension Supported
Advanced Cryptography Engine Not Supported
Alternate Instruction Set Not Supported
Automatic Clock Control Supported
CPL Qualified Debug Store Not Supported
Debug Trace Store Supported
Debugging Extension Supported
Enhanced SpeedStep Technology Not Supported
Fast Save & Restore Supported
Fast System Call Supported
Hyper-Threading Technology Not Supported
L1 Context ID Supported
Local APIC On Chip Supported
LongRun Not Supported
LongRun Table Interface Not Supported
Machine-Check Architecture Supported
Machine-Check Exception Supported
Memory Type Range Registers Supported
Model Specific Registers Supported
No-Execute Page Protection Not Supported
Page Attribute Table Supported
Page Global Extension Supported
Page Size Extension Supported
Pending Break Event Supported
Physical Address Extension Supported
Processor Duty Cycle Control Supported
Processor Serial Number Not Supported
Random Number Generator Not Supported
Self-Snoop Supported
Thermal Monitor Supported
Thermal Monitor 2 Not Supported
Time Stamp Counter Supported
Virtual Mode Extension Supported
CPUID Registers:
CPUID 00000000 00000002-756E6547-6C65746E-49656E69
CPUID 00000001 00000F29-0001080A-00004400-BFEBFBFF
CPUID 00000002 665B5101-00000000-00000000-003B7040
CPUID 80000000 80000004-00000000-00000000-00000000
CPUID 80000001 00000000-00000000-00000000-00000000
CPUID 80000002 20202020-20202020-20202020-20202020
CPUID 80000003 65746E49-2952286C-6C654320-6E6F7265
CPUID 80000004 20295228-20555043-30342E32-007A4847
MSR 00000017 000A-0000-0000-0000
MSR 0000002C 0000-0000-1810-0018
--------[ Motherboard ]-------------------------------------------------------------------------------------------------
Motherboard Properties:
Motherboard ID 62-5900-001169-00101111-040201-I845E$16566E00A6566IMS V5.9 090103
Motherboard Name MSI 845E Max (MS-6566E)
Front Side Bus Properties:
Bus Type Intel NetBurst
Bus Width 64-bit
Real Clock 100 MHz (QDR)
Effective Clock 400 MHz
Bandwidth 3200 MB/s
Memory Bus Properties:
Bus Type DDR SDRAM
Bus Width 64-bit
Real Clock 133 MHz (DDR)
Effective Clock 267 MHz
Bandwidth 2133 MB/s
Chipset Bus Properties:
Bus Type Intel Hub Interface
Bus Width 8-bit
Real Clock 67 MHz (QDR)
Effective Clock 267 MHz
Bandwidth 267 MB/s
Motherboard Physical Info:
CPU Sockets/Slots 1
Expansion Slots 6 PCI, 1 AGP, 1 CNR
RAM Slots 2 DIMM
Form Factor ATX
Motherboard Size 200 mm x 300 mm
Motherboard Chipset i845E
Extra Features Fuzzy Logic 4
Motherboard Manufacturer:
Company Name Micro-Star International
Product Information http://www.msi.com.tw/program/products/mainboard/mbd/pro_mbd_list.php
BIOS Download http://www.msi.com.tw/program/support/bios/bos/spt_bos_list.php
--------[ Memory ]------------------------------------------------------------------------------------------------------
Physical Memory:
Total 127 MB
Used 75 MB
Free 51 MB
Utilization 59 %
Swap Space:
Total 307 MB
Used 144 MB
Free 163 MB
Utilization 47 %
Virtual Memory:
Total 435 MB
Used 220 MB
Free 215 MB
Utilization 51 %
Problems & Suggestions:
Suggestion Install more system memory to improve applications performance.
--------[ SPD ]---------------------------------------------------------------------------------------------------------
[ 256 MB PC2100 DDR SDRAM ]
Memory Module Properties:
Serial Number 00303430h
Module Size 256 MB (1 rows, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC2100 (133 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Normal (15.625 us), Self-Refresh
Highest CAS Latency 2.5 (7.5 ns @ 133 MHz)
2nd Highest CAS Latency 2.0 (10.0 ns @ 100 MHz)
Memory Module Features:
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
--------[ Chipset ]-----------------------------------------------------------------------------------------------------
Chipset Properties:
Motherboard Chipset Intel Brookdale i845E
In-Order Queue Depth 12
CAS Latency 2.5T
RAS To CAS Delay 3T
RAS Precharge 3T
RAS Active Time 6T
AC'97 Audio Controller:
Audio Controller Type Intel 82801DB(M) ICH4
Codec Name Avance Logic ALC655/ALC850
Codec ID 414C4760h
Memory Slots:
DRAM Slot #1 512 MB (PC2100 DDR SDRAM)
AGP Properties:
AGP Version 2.00
AGP Status Enabled
AGP Aperture Size 64 MB
Supported AGP Speeds 1x, 2x, 4x
Current AGP Speed 4x
Fast-Write Supported, Enabled
Side Band Addressing Supported, Enabled
Chipset Manufacturer:
Company Name Intel Corporation
Product Information http://www.intel.com/products/browse/chipsets.htm
Driver Download http://support.intel.com/support/chipsets/index.htm
Problems & Suggestions:
Problem AGP aperture size is more than half of the system memory size. This may cause performance penalty.
--------[ BIOS ]--------------------------------------------------------------------------------------------------------
BIOS Properties:
BIOS Type AMI
System BIOS Date 09/01/03
Video BIOS Date 08/18/03
BIOS Manufacturer:
Company Name American Megatrends Inc.
Product Information http://www.ami.com/amibios -
IdeaCenter B305 "DQS training failed" message on startup
I have a IdeaCentre B305 40312CY, suddenly it began giving a message:
"DQS training failed on previous boot, reverted to slower DRAM speed
Press F1 to enter Setup, F2 to resume"
Now the problem is that if I press F1, first an "Entering Setup" message then a "WAIT..." message appears on the middle of the screen and nothing more happens.
If I press F2 the HD is detected, then a "CMOS Battery Low" message and then again "Press F1 to Run Setup" "Press F2 lo load default values an continue". Let say that here F1 gives de same WAIT... message as before and with F2 a column of "H" appear on the left side of the screen.
I test the CMOS battery and it was OK, even though I change it with a new one with no results. I also tried to reset de CMOS with the motherboard jumper but nothing happens.
Does the computer have a problem with the BIOS ? What can I do ? The computer is already out of warranty.
Please Help !!!hi xpeed,
Welcome to the Forums.
As per these articles:
http://wiki.answers.com/Q/What_is_DQS_in_ddr3_sdram#slide3
"When the data is read from the DRAM using the DQ pins, DQS (Data Strobe) is asserted so that the memory controller can use that to read data."
http://www.latticesemi.com/lit/docs/generalinfo/memory_ddr_interface_wp.pdf
"DDR SDRAM interfaces rely on the use of a data strobe signal called DQS. DQS is generated from the differential
clock fed to the DDR memory and a DLL inside the DDR memory used to generate and align DQS to outgoing data."
The "DQS training failed" that your getting is somehow related to the memory timings on how data is written to the DRAM and on how the data is read by the memory controller. It's possible that the RAM, the CPU's memory controller or the memory controller in the Northbridge is having issues. Have you tried to reseat or change the RAM?
The "CMOS Battery Low" message might indicate an imminent failure on the CMOS Battery but since you already changed it, are you still getting the "CMOS battery low" error when pressing F1 to go to the BIOS? If not then you may need to isolate the DQS error above.
Regards
Did someone help you today? Press the star on the left to thank them with a Kudo!
If you find a post helpful and it answers your question, please mark it as an "Accepted Solution"! This will help the rest of the Community with similar issues identify the verified solution and benefit from it.
Follow @LenovoForums on Twitter! -
IO fails working for low frequency, but work well for higher frequency
On our customized VU440 board, we did a IO performance test for each bank and found a strange problem, in the design,we send out 24bits Pseudo random data and loop back this data to the same bank with our testing board, on which the pins for tx and rx are only connected in short circuit, one differential clock is transfered to single-ended global clock in the design, using IBUFDS+BUFG to provide the global clock for tx module and rx module.
howeve, we use vivado debug tool to check the data looped back, only found when the clock is 200MHz around, the data is correct, but if fails to get correct data when the clock is much lower, for example, 10MHz ~100MHz. And from the waveform we got, we identified the status for some pin was un-normal when the data bus failed to get correct data.
we have found the problematic IO pins, but did not know why the problem come out, normally, we think it's normal for the IO pins fail to work when the frequency is too high, but in our case, the issue is on the contrary, we don't understand why it works for some higher frequency but fail to run when it's much lower.
we now try to check our PCB also, but have no clue at present.
Some guys have any idea or suggestion to check for the reason?
thx~Hi,
What is the IO standard that you selected for the TX and the RX. How long is the loopback cable?
Do you have proper terminations on the board? Because in general, all IO Standards need some terminations which are mentioned in the respective SelectIO user Guide for that device. Please check that. -
Is the bit file the programming file?
Hi all
I have a design that came to me as part of an evaluation board from a vendor. The vendor's design has something like 10 clocks, most derived from a single input clock using PLLs and DCMs. Their UCF has very few timing constraints (shown below), but ISE finds 4 violations of constraints that Timing Analyzer must arrive at on its own. Some seem pretty serious (-5ns slack sounds like a lot to me), BUT: ISE generates a new bitfile anyway!
Main question: Is the bitfile being generated because the failures aren't due to explicit constraints?
(One more twist, maybe: The bitfile generator fails, and blames these timing violations, if I try to include an ILA. It also refuses to open the contraints editor until I remove the ILA from the design. I've seen a couple of threads in this forum that gave me some ideas, so I'm going to try some things and open a separate thread if I can't resolve this myself).
from the UCF:
## TIMING CONSTRAINTS
NET "clk_100m_p" TNM_NET = "clk_100m_p";
TIMESPEC "TS_clk_100m_p" = PERIOD "clk_100m_p" 10 ns;
INST i_tsc_cmv12000_clocking/SRL16_inst/SRL16E TNM = TNM_SLR16;
INST "rb1*" TNM = TNM_RB;
TIMESPEC TS_RB = FROM TNM_SLR16 TO TNM_RB 10 ns;
INST "i_tsc_cmv12000_clocking/SRL16_inst/SRL16E" TIG=TS_clk_100m_p;
NET "clk_rx_p" TNM_NET = "clk_rx_p";
TIMESPEC "TS_clk_rx_p" = PERIOD "clk_rx_p" 3.33 ns;
'clk_100m_p' is the + side of the differential input for the clock everything else is derived from.
'INST i_tsc_cmv12000_clocking/SRL16_inst/SRL16E TNM' refers, I think, to a DRP-controlled PLL, or to the FIFO that queues commands to it. 'rb1*' refers to the register bank that runs everything in the FPGA.
'clk_rx_p' is the + side of a differential clock output to another component.
Main question: Is the bitfile being generated because the failures aren't due to explicit constraints?
The tools do not prevent bitfile generation due to failure to meet timing.
The bitfile generator fails, and blames these timing violations, if I try to include an ILA
I've never encountered that.
-
875P NEO FIS2R with Corsair TwinX1024-4000
Hi there,
My first post, not sure if it should be here or in the Intel P4 based board forum, but we'll start here.
System posted in signature (hopefully )
I've tried to read as much as possible on the compatibility issues, but cannot find anyone who has experienced quite the same thing.
The Problem:-
I cannot get my Corsair TwinX1024-4000 memory to run at its rated 500 MHz.
The main reason for this appears to be that no matter what BIOS settings I use the CAS # Latency will not go above 2.5 cycles. Consequentially, my memory will not clock above 230 MHz (DDR 460 MHz).
I currently have the BIOS set to manually force 3-4-4-8 + 8 burst, but CPU-Z still reports 2.5-4-4-8. DOT is off, Performance mode is slow. Memory Voltage is 2.75V.
I appreciate that the SPD configuration of these is PC3200 and therefore AIDA32 reports:-
Quote
Memory Module Properties
Module Name Corsair CMX512-3200C2
Serial Number None
Module Size 512 MB (2 rows, 4 banks)
Module Type Unbuffered
Memory Type DDR SDRAM
Memory Speed PC3200 (200 MHz)
Module Width 64 bit
Module Voltage SSTL 2.5
Error Detection Method None
Refresh Rate Reduced (7.8 us), Self-Refresh
Highest CAS Latency 2.5 (5.0 ns @ 200 MHz)
2nd Highest CAS Latency 2.0 (6.0 ns @ 166 MHz)
Memory Module Features
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Not Supported
On-Card PLL (Clock) Not Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
Memory Module Manufacturer
Company Name Corsair Memory, Inc.
Product Information http://www.corsairmicro.com/main/products.htm
I know that some people have reported issues with loading all 4 channels with the 875, but I have tested with 1, 2, and 4 modules and it makes no difference to this issue. The only thing I see is a memory bandwidth change (Sandra 2004 - single channel approx. 4000 Mb/s, Dual Channel approx. 5300 Mb/s, Quad Channel approx. 5150 Mb/s)
So cutting to the chase, why can I not force CAS # Latency = 3???
I have recently tried the 1.9beta , but it would not post past "Checking NVRAM" for me, so have returned to pukker 1.9.
I have 4 other MSI based systems that work a treat, so I'd hate to have to go buy an ASUS to get my memory to work.
Any help will be greatly appreciated.
Best Regards,
Ed!I agree that the memory "optimization" attempt by MSI for the 875 causes a great deal of suffering for all of us who use the MOBO. But I encourage you to bide your time a little longer, before pumping another couple hundred bucks into a second board. I have read an almost unimaginable (and probably unhealthy) amount of data about the Memory Substructure of the 875 MOBOS and their various compatibility quirks w/ different RAM. And I spend damn-near as much time in the other MOBO makers' forums as in this one! All of this observation/research plus the lessons I have absorbed at the feet of "THE REILLY875" , have convinced me that all of the boards have serious potential fubars depending on a vast number of variables. If you were looking to buy your 1st 875 MOBO, I think that ASUS or ABIT would be the best/safest/highest OC performance choices. But as you already have the MSI, I think that the "smart money" favors sitting tight for another BIOS update and/or new RAM models which might be designed w/ the various memory compatibility problems in mind. Besides, it is possible to get a mid-range OC w/ the current MSI 875, you just need really good 3500, or 4000+ RAM. I'd hate to see you switch boards only to encounter one of the documented problems w/ the other 875 MOBOS, followed by a (I'm trying to be veeeeery positive here!) fixed/optimized BIOS from MSI. Whichever you chose, brother, I'm happy to help any time!
damon69 -
K7D Master + 4GB RAM- New problem
Hi this is my setup:
Dual AMD Athlon MP-A, 2133 MHz (8 x 267) 2800+ Barton A2
Motherboard Properties
Motherboard ID 10/09/2003-AMD762-W83627-6A6S7M49C-00
Motherboard Name MSI K7D Master (MS-6501) (bios v. 1.91- newest)
Front Side Bus Properties
Bus Type DEC Alpha EV6
Bus Width 64-bit
Real Clock 133 MHz (DDR)
Effective Clock 267 MHz
Bandwidth 2133 MB/s
Memory Bus Properties
Bus Type DDR SDRAM
Bus Width 64-bit
Real Clock 133 MHz (DDR)
Effective Clock 267 MHz
Bandwidth 2133 MB/s
Chipset Bus Properties
Bus Type PCI
Bus Width 32-bit
Real Clock 33 MHz
Effective Clock 33 MHz
Bandwidth 133 MB/s
My problem is that the motherbord can see only 3670016k RAM with all 4 dimms plugged
I have checked by changing setup several times that all modules and slots are working.
I addictionally checked SPD, and found that all modulles are visible as 1024.
I use Transcend TS128MDR72V6A
Memory Module Properties form (SPD)
Module Name Transcend TS128MDR72V6A
Serial Number 00011DA2h
Module Size 1024 MB (2 rows, 4 banks)
Module Type Registered
Memory Type DDR SDRAM
Memory Speed PC2100 (133 MHz)
Module Width 72 bit
Module Voltage SSTL 2.5
Error Detection Method ECC
Refresh Rate Reduced (7.8 us), Self-Refresh
Highest CAS Latency 2.5 (7.5 ns @ 133 MHz)
2nd Highest CAS Latency 2.0 (10.0 ns @ 100 MHz)
Memory Module Features
Early RAS# Precharge Not Supported
Auto-Precharge Not Supported
Precharge All Not Supported
Write1/Read Burst Not Supported
Buffered Address/Control Inputs Not Supported
Registered Address/Control Inputs Supported
On-Card PLL (Clock) Supported
Buffered DQMB Inputs Not Supported
Registered DQMB Inputs Not Supported
Differential Clock Input Supported
Redundant Row Address Not Supported
I have also foud that info from chipset is wery strange- showing some non existing 5-th memory slot.
This is the info
Chipset Properties
Motherboard Chipset AMD-760MPX
CAS Latency 2.5T
RAS To CAS Delay 3T
RAS Precharge 3T
RAS Active Time 6T
Memory Slots
DRAM Slot #1 1024 MB (Registered ECC DDR SDRAM)
DRAM Slot #2 1024 MB (Registered ECC DDR SDRAM)
DRAM Slot #3 1024 MB (Registered ECC DDR SDRAM)
DRAM Slot #4 512 MB (Registered ECC DDR SDRAM)
DRAM Slot #5 256 MB (Registered ECC DDR SDRAM)
There should be 1024 MB module indicated in slot #4 - but insted there is some s....
What can be wrong? I'm getting mad cause This Transcend modules cost me a fortune - and i bought it cause i really need it... all four!!!This is from the Tyan mainboard web site
http://www.tyan.com/products/html/tigermpx_spec.html
* Note: The AMD-760 MPX requires a portion of memory to be reserved for PCI devices. Allocation for these devices is dependent on the number of PCI devices installed, and option ROM for each device. Common configurations will see 3.5GB to 3.8GB of available memory.
Several brands of mainboard say this unless they support more than 4GB.
MSI does not mention this on their web site or in the manual.
I suspect the only solution is to get a mainboard that supports 6GB or more.
Maybe you are looking for
-
Image processing from .txt file onto an intensity graph
I am doing a mini project in my class and I was wondering if anyone could help me. It about image processing but I am bit stuck. Heres the idea: "An image is really nothing more than a 2D array of data. The value of every element in the array corresp
-
hello, I need to cancel technical completion for an order with BAPI BAPI_ALM_ORDER_MAINTAIN, How can I call this ? Could you please help me ? Thanks
-
I'm working on a pdf for limited distribution. It appear that my options for securing a pdf is limited to this (using only Acrobat software): 1) password protecting it (1 or 2 levels depending on whether or not I want people to be able to fill out f
-
Cannot setup email on C7 with Belle
Hello, I recently updated my C7 to Belle and when I try to create an email account for my yahoo account, the only type of email that is proposed to me is Exchange ActiveSync. How can I create an email account to access my yahoo emails?
-
What software is available for MacOSX that comes closest to performing like the old Appleworks drawing program?