CRio FPGA read 1024000 samples and transfer to RT

Hello,
I have a cRIO application and i have to read 1024000 samples, on 3 channels at a sampling rate of 25.6 khz.. My NI 9232 offers the posibility of sampling at such a rate. The problem is that i do not know how to aquire and transfer that amount of data to the RT. I'd be grateful if someone could help me.
Attachments:
FPGA.vi ‏60 KB
RT.vi ‏359 KB

Valentina,
You are correct to mention that your data will not be continuous with the abort node. I only mentioned that you should use the abort node because your FPGA VI was not sampling continuously and you were restarting the FPGA from the RT target.
If I understand your application correctly, you’d like to continuously analyze a set of 1024000 samples on the RT target. Is this correct?
If so, why are using a For Loop to read from the AI node only N times (where N = Samples per Channel)? Why not place the AI node and FIFO Write method in a while loop, as done in the Streaming Data (DMA).lvproj example, which you can find in the LabVIEW Example Finder? By placing these nodes in a while loop, you’ll get a continuous stream of data from the FPGA until you tell the while loop to stop.
On the RT side, you can also use a while loop to continuously read the data in the FIFO. If reading 1024000 samples from the FIFO at once does not work for you, you should consider setting the number of elements to read from the FIFO to a value where 1024000 is a multiple of it. This approach might take a little more work because you have to join N iterations of the FIFO data together in order to pass a set of 1024000 samples to your analysis function.
Regards,
Tunde S.
Applications Engineer
National Instruments

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DigitalNSample.vi ‏27 KB
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------------Task summary:
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I have a few questions / observations for you based on your post:
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Thanks for replying. To answer your first question: I'm transferring to a desktop computer. The controller is able to connect with a PCI express x16 slot in the desktop computer. I'm not sure how to technically describe it, but the controller plugs into the PXIe chassis, then there is another card that plugs into the host computer's PCI express x16 slot, and finally there is a large cable that connects the card in the host computer and the controller.
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I have a question about the 7966R vs the 7975R that you mentioned. I could probably find the information in the specifications, but I figured I would just ask you here. Is there any advantage to using the 7966R over the 7975R in terms of programmable logic elements? From what I could quickly read, the 7975R has more DSP slices and RAM, but does it have less general purpose logic blocks than the 7966R? The reason I'm asking is because the project that I'm working on will eventually involve implementing as much signal processing on the FPGA as possible. But obviously figuring out the acquisition part of the project is more important right now.
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Hi Michael,
A few updates to my previous post:
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Andrew T.
National Instruments
I'll go ahead and respond to your latest response too. Thanks again for your help.
I think I understand the streaming rate concept. I'm not using time interleaved sampling. My application requires using the simultaneous sampling mode. I need two channels of input data.
Unfortunately I don't think I can sacrifice on bit depth. But for right now I can probably sacrifice half of the sampling rate, and reduce my acquisition duty cycle from 100% (constantly streaming) to 50% (acquiring only half of the time). My acquisition rate will still need to be 50kHz though. I'm planning to compromise on sampling rate by summing pairs of data points instead of simply decimating, and then transferring the data to the host.
Questions:
We (my advisors and I) think that the summing pairs approach would preserve more information than simply throwing away every other point. Also, we can avoid overflow because each 16-bit number only contains 12-bits of actual information. The 16-bit number will just need to be divided by 16 before summing because the 12-bits of information are placed in the 12 MSBs of the 16-bit number. Does that sound right?
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[Screenshot]
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Message Edited by Kennie87 on 02-16-2009 09:23 AM
Message Edited by Kennie87 on 02-16-2009 09:23 AM
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lvrt_err_log.txt ‏23 KB

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Craig H. | CLA | Systems Engineer | National Instruments

Log and Transfer with Panasonic HD

Recently I purchased the Panasonic HDC-HS 100, which is a hybrid SD card/HDD, (AVCHD). I use the Mac OS X (10.4.11) with Final Cut Pro 6.0.5. I am having problems importing my footage onto my computer. When opening the log and transfer window in FCP, it does not recognize the camera (error messages indicate there is an invalid directory structure). Also, the media has been saved to my computers hard drive. How do I get this footage on my computer so I can start editing! Thanks for the help.

Do you have an external card reader? Or are you playing back from the camera? When you copied the contents of the card to the computer, did you copy the whole card, or just the video clips? You have to copy the ENTIRE card, as is. Create a folder on your external hard drive and name it P2(name of project)#. So if you have 3 cards you used for the project "My Haircut" you would have 3 folders named
P2myHaircut-1
P2myHaircut-2
P2myHaircut-3
That is just a sample naming scheme. You can use what you want, just be consistent so you can find your footage easily. Then, mount your SD card on the desktop, open it, select all, and drag to the appropriate folder. Make sure you select all. Then, open Log and Transfer, go to the upper right corner of the Log and Transfer browser and click on the drop down button. You will see a choice that says Create Custom Path. Click that, then locate the Folder you just created. Click once on that folder and then "choose". DON'T choose the internal folders, just choose your P2myHaircut# folder. You should see your clips pop up in that browser. If this doesn't work, you may be missing a component for that camera. Honestly, I don't know anything about your camera, but that is the process for Log and Transfer.

FPGA Read/Write Control Function Issues

Hello all! Rather new to using FPGA, but I have an interesting issue that's popping up.
Currently pulling in RAW voltage data from a set of sensors (Pressure Transducers, Load Cells, etc) through a cRIO DAQ. Have the FPGA file setup to pull in that data already and have the main VI and all the sub-VIs working just fine.
What I'm trying to do is save the raw voltage data (TDMS files) on the lower level and the convert and display on the upper level so that I don't have to convert and save (speed up saving data). So that leaves 3 distinct "levels/sections":
On FPGA that pulls in the raw data
On FPGA that saves the raw data
Main VI that does all the controls/conversions/displays etc.
Number two is where I'm having an issue. I want to save all the data in parallel so I'm creating a save FPGA for the I/O devices (8 Relays to command solenoid valves, 3 Pressure Transducers, 1 Load Cell, 4 Thermocouples).
The issue I'm having is when I use the FPGA Read/Write control to read in from the Target and save to the TDMS. When I only use a single FPGA target reference the lines are broken, but as soon as I switch to two targets, it now works.
I've attached a screen cap of the current problem. The set-up on the bottom (with only one target) doesn't work. But the second I add more than one target, it works.
Any reason why it might be doing this? Any ideas/suggestions at all on how to go about setting this up in general?
Thanks!
Attachments:
FPGAError.jpg ‏35 KB

HySoR,
You might check the documentation for "data" terminal of "TDMS Write" (http://zone.ni.com/reference/en-XX/help/371361H-01/glang/tdms_file_write/). One DBL element is not accepted, but 1D DBL array is accepted.
data is the data to write to the.tdmsfile. This input accepts the following data types:
Analog waveform or a 1D array of analog waveforms
Digital waveform
Digital table
Dynamic data
1D or 2D array of:
Signed or unsigned integers
Floating-point numbers
Timestamps
Booleans
Alphanumeric strings that do not contain null characters

CRio FPGA read 1024000 samples and transfer to RT

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