[cRIO] FPGA compile time

Question

Hello, I was wondering the normal time for LabVIEW to compile a program for cRIO FPGA target.
It has been taking 15 minutes per compile. I was wondering whether this is normal or whether there
is something I could do to make it faster. 
- Thank you 

Answer 1

This is the compile report of the code I am working with:
Status: Compilation successful.
Compilation Summary
Logic Utilization:
  Number of Slice Flip Flops:       5,531 out of  40,960   13%
  Number of 4 input LUTs:           5,475 out of  40,960   13%
Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 8      25%
      Number of LOCed BUFGMUXs               1 out of 2      50%
   Number of External IOBs                 164 out of 333    49%
      Number of LOCed IOBs                 164 out of 164   100%
   Number of MULT18X18s                     14 out of 40     35%
   Number of Slices                       3874 out of 20480  18%
      Number of SLICEMs                      4 out of 10240   1%
Clock Rates: (Requested rates are adjusted for jitter and accuracy)
  Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Theoretical Maximum: 54.191730MHz
  Base clock: MiteClk (Used by non-diagram components)
      Requested Rate:      33.037101MHz
      Theoretical Maximum: 61.406202MHz
Start Time: 9/18/2008 12:13:18 PM
End Time: 9/18/2008 12:29:22 PM
This is the compile report if I delete most of the code.
It only has a while loop and I/O pin read and write, and an inverter.
[Screenshot]
Status: Compilation successful.
Compilation Summary
Logic Utilization:
  Number of Slice Flip Flops:         583 out of  40,960    1%
  Number of 4 input LUTs:           1,021 out of  40,960    2%
Device Utilization Summary:
   Number of BUFGMUXs                        2 out of 8      25%
      Number of LOCed BUFGMUXs               1 out of 2      50%
   Number of External IOBs                 164 out of 333    49%
      Number of LOCed IOBs                 164 out of 164   100%
   Number of Slices                        671 out of 20480   3%
      Number of SLICEMs                      4 out of 10240   1%
Clock Rates: (Requested rates are adjusted for jitter and accuracy)
  Base clock: 40 MHz Onboard Clock
      Requested Rate:      40.408938MHz
      Theoretical Maximum: 85.113627MHz
  Base clock: MiteClk (Used by non-diagram components)
      Requested Rate:      33.037101MHz
      Theoretical Maximum: 70.566650MHz
Start Time: 9/18/2008 2:00:03 PM
End Time: 9/18/2008 2:12:19 PM