CRIO; To FIFO or no to FIFO?

That is my question.
My project is using a cRIO-9073 There are three analog input modules. Two analog output modules, and one relay output module. All are running in Scan Mode.
Currently I have the chassis with the modules installed on my desk. But I am not connected to any real world IO.
I've done some initial testing with the host and target and I am now creating IO Alias Variables that I will use in my code. However, I'm a little unsure about the types of variables I should be using for this project. IO Alias Variables do not have the option of FIFO or any buffering that I can see. But I'm not sure if I require that or not.
The project will have some monitoring and controls done on the RT Target. A couple of the analog inputs will be set to trigger digital outputs if they rise above a setpoint.
The host will log all inputs to a database and keep a circular buffer of data in memory for display on a "live" graph. There will also be some manual controls and access to the setpoints that the RT Target will use.
The process is slow. The fastest data will be logged is once per second and nothing needs to react any faster than that.
So far, it seems very easy for me to just use my IO Alias Variables either on my Target in or my Host. I would think that at the speed things will be operating, this method would be more than sufficient. However we have a very short development cycle planned for this project and I'd really like to avoid any potential problems.
Can anyone with some experience tell me why this method may or may not have problems?
Muchly appreciated.
Patrick Allen
Solved!
Go to Solution.

Patrick,
If the samplings rates of your application are as you stated in your post, there really is no need to switch to FPGA mode. Scan mode should be more than sufficient to get you all the data. Keep in mind you can go up to about 1Khz rate using Scan mode (given that your modules are capable of those rates). Also, using the Scan mode I/O variables are by far the easiest way to get your data over to the host. You actually just drag and drop the IO variables corresponding to your modules' physical channels directly into your PC Host VI. Overall, I don't see any problems with your design so far, but at the same time, you did not elaborate too much on the requirements of the project.
If you're looking for more information about the cRIO Scan Mode, I suggest the following:
Using NI CompactRIO Scan Mode with NI LabVIEW Software
The RIO Scan Interface Under the Hood
Cheers,
Misha

Similar Messages

FIFO implementation after go-live: implications on existing data and ML

Hello All,
We have a client who wishes to implement a FIFO stock management approach. They have been working on SAP for a few years now. I would like to know how we would 'cutover' to a FIFO stock valuation method? Would executing MRF3 for a date range be sufficient?
Also, please could you advise whether there are any discussion documents on the impact this change would have on actual costing using the material ledger, which they are currently using?
Thank You in advance for any assistance.
Kind regards
AMS

Hi!
you have to do following customization for LIFO/FIFO valuation:
Go to Material Management->Valuation & account assignment ->BS valuaiton procedures ->Configure LIFO/FIFO methods:
1.activate LIFO/FIFO
2. Define valuation levels
3. exclude online update
4.define relevant movement types for LIFO/FIFO
5.define LIFO/FIFO methods - in order to calculate FIFO price for current period , previous period, previous to previous period and previous year.
6.configure FIFO vlauation areas - here you have define base year as per your requirement
then you can able to do FIFO valuation - t.codes MRF4, MRF3,MRF1- u can update FIFO price in material master other than std price & MAV price fields.
there is no impact on actual material ledger. this is only used for balance sheet valuation purpose based on requirement.
Please let me know if you need any further clarificaitons
regards,
ramesh B

FIFO Valuation with Material Ledger !

Hi,
How do we accomplish FIFO Valuation using Material Ledger ?
We have activated the Material Ledger, with Single - Level Determination; Standard Price S. On execution of Single-Level Price Determination, we get the Periodic Unit Price -- which is the Weighted Average Price for the Receipts for the period involved.
I came across SAP Forums, which claim that Material Ledger is the FIFO Valuation on real-time basis. However, this doesn't seem to be true. The Goods Issued are assigned the Periodic Unit Price (calculated above -- i.e the Weighted Average Price ).
In addition, we have Configured the FIFO Balance Sheet Valuation Procedure, through the MM menu. The FIFO Value for the Material is giving weird results. Adding the total Inventory for all the Receipts till date and over-riding the period selection for Single Receipts. For monthly receipts, the system just gives the Weighted Average Price again.
The Business is expecting the FIFO valution for the Inventory Balance on Monthly Basis. ( We are using Material Ledger, so that we can roll-up this FIFO Valuation of the Raw Material ito Gross up into the Finished Product
-- Thanks

Hi Kenny ,
BASIC STEPS THAT CAN BE FOLLOWED FOR ENDING INVENTORY VALUATION :
Ending Inventory is valued as per FIFO calculated through following steps:
     Run the price calculation (Txn: KSII) u2013 check that all      auxiliary Cost centers are zero
     Run Txn:MRF3 (summarization of documents for the      FIFO calculation.)
     Run MRF1 (calculation of FIFO)
     Check if the FIFO calc. is correct via MR35
After ML run the ending inventory value should be equal to the value in MR35 and so balance amount not yet loaded to ending inventory through FIFO valuation is posted to consumption
Exception: If total receipts for a period is less than ending inventory quantity .In this case the EI is valued at weighted average
Please check wether the steps have been properly followed and the execption doesnot exists..
Also, hope your Price Determination is "3" and price control is "S" in Material Master..
Regards
Sarada

Query for a list of FIFO layers with quantity and FIFO cost

Hi,
Is there a report/ query where I could get something as follows:
ItemCode1 - Open FIFO Layer1 - Quantity 1 - Open FIFO Layer1 Cost - Open FIFO Layer1 Inventory Value
ItemCode1 - Open FIFO Layer2 - Quantity 2 - Open FIFO Layer2 Cost - Open FIFO Layer2 Inventory Value
ItemCode1 - Open FIFO Layer3 - Quantity 3 - Open FIFO Layer3 Cost - Open FIFO Layer3 Inventory Value
The total quantity and the total value of this would match the total quantity and total value of the Inventory Audit Report.
I know OINM table has all detailed transactions, but I find it difficult to get what I want from OINM.
Thanks,
Ajay Audich

Hi Ajay.....
Please do refer Inventory Valuation Simulation Report for FIFO Method. It gives you the details as you required........
Regards,
Rahul

Mélange de données dans une FIFO ?

Bonjour à tous,
je me retrouve confronter à un problème qui après une journée de recherche reste un mystère pour moi...
Voilà le tous:
Pour commencer je récupère des valeurs depuis trois entrée analogique d'une carte 9222 du coté FPGA, et les assemble dans un tableau pour les transférer via une FIFO:
Dans l'indicateur du tableau, je vois que les données sont bien rangées {Ic,Uc,Cw}.
Je récupère donc ensuite ces données du coté RT:
Et là, surprise !!!! Toutes les données sont dans le désordre... et de manière aléatoire, sinon c'est pas drole...
Sachant que si elles sont rangées correctement je les récupère à l'aide de la fonction "Décimer un tableau 1D".
Quelqu'un aurait-il une solution ou se serait déjà confronter au problème ?
Cordialement,
Nathan
Résolu !
Accéder à la solution.

Si on prend le sens FPGA->Host, les données seront acheminées vers le buffer côté Hôte dès qu'il y aura de la place (par défaut le buffer est de 10000 éléments, reconfigurable). Le but est donc de lire la FIFO jusqu'à ce qu'il n'y ait plus rien, sachant qu'on n'écrit pas côté FPGA. On peut aussi vider la FIFO FPGA avec un FIFO Flush (dans le code FPGA). Les FIFOs FPGA sont aussi vidées lorsque le FPGA fait un reset, typiquement lorsque qu'on appelle la fonction Close FPGA Reference ou par appel explicit du noeud de méthode Reset côté Hôte...
Bref, il existe plusieurs méthodes, à adapter en fonction de l'application
Eric M. - Application Engineering Specialist
Certified LabVIEW Architect
Certified LabWindows™/CVI Developer

Coding cRIO 9402 DIO on FPGA

Hi guys,
I am writing an application for the following hardware;
Controller - cRIO 9022
Chassis - cRIO 9114
Modules - 9402 DIO, 9213 Thermocouple I/P, 9205 AI
The 9213 and 9205 are both taking low frequency measurements so I plan using the scan interface for these modules.
One channel of the 9402 will be required to determine the frequency of a digital signal at ~4 MHz so I will have to code this using the FPGA interface. Two other channels will be required to output low frequency digital signals.
I have looked at the Count and Period (FPGA) example in the example finder;
In my application, instead of generating the pulse train, would the 'Digital Signal' in the timed loop be replaced with an I/O node? And the While Loop removed?
How could I expand this to write Boolean values (communicated from the host vi) to 2 other outputs?
I have read the cRIO Developers Guide which uses DMA FIFOs to communicate between Host and FPGA, would I require multiple DMA FIFOs? This is the first application I have written for a cRIO target so any and all tips/references are appreciated
Many thanks,
Pete
Regards,
Peter D

Hi Dan,
Thank you for the reply.
I was planning on running in Hybrid Mode as you mentioned, although you're probably right that coding straight to the FPGA will avoid some hiccups.
I will interleave the analogue inputs and thermocouple inputs as these are both measurements taken at similar frequencies.
I had a quick go at making a host and FPGA VI to the analogue inputs from the AI and Thermo modules;
FPGA.vi
Host.vi
This doesn't run at the moment but I think it's because I'm simulating the hardware, as it arrives early next week. I still have a couple of questions about how to expand this to include the digital module.
If I want a 'Digital Acquisition' loop to run on the FPGA at a different sample rate to I just make another loop with a lower 'Data Rate' constant?
How would I then read from the new DMA FIFO on the host VI?
I think the reason I am having trouble is that I can't find examples which have multiple IO running on the FPGA at different sample rates.
Thanks again,
Pete
Regards,
Peter D

CRIO disconnects from Ethernet network and stops responding to pings

We are running a cRIO application that periodically disconnects from the Ethernet network even though the VI continues to run on the cRIO.
The application has two parallel loops. One loop reads data from the FPGA and writes it to a RT FIFO. The second loop opens a TCP connection to a remote host, reads data from the RT FIFO, and transmits the data to the remote host. We have instrumented each loop to send messages to the serial port that indicate their status. When the cRIO disconnects, both loops continue to send their status messages to the serial port. The first loop happily continues reading data from the FPGA and writing it into the RT FIFO. The RT FIFO overwrites the oldest data when it fills up to keep it from overflowing. The second loop reports a TCP write timeout (tcp write error 56) around the time that the cRIO disconnects, after which it closes the existing TCP connection and then repeatedly tries to open a new TCP connection (each attempt times out after a 5 second delay).
All that appears normal and usually the connection is automatically restored. Occasionally, however, the cRIO is not able to re-open the TCP connection. Furthermore, the cRIO stops responding to pings from the remote host. On two occasions, the cRIO was finally able to open a new connection after 30-40 minutes. Other than that, the only way we've found out of this dilemma is to reboot the cRIO.
The frequency of the disconnects and the time before they occur doesn't seem connected to whether or not the cRIO is set to run the application at startup or if the application is run via an interactive VI window on the remote computer.
It is possible that the disconnects have something to do with which computer the cRIO is connected to, as the problems seem to happen much more frequently (often within minutes) when the cRIO is sending data to a laptop running Windows XP, but it can run for hours when sending data to a rackmount server running Windows Server 2003. Everything else (the speed and size of data being sent, the ethernet hub and cables, the VI running on the remote computer) is the same.

We're done most of the testing with a 9014 real time controller and a 9104 chassis. However, we've also seen similar behavior with 9014/9103 and 9102/9101 combinations.
The 9014 cRIO normally runs at around 50% CPU usage and less than 40% memory usage when the data is flowing steadily. The RT System Monitor did not indicate a spike in either before the cRIO disconnected.
Measurement and Automation Explorer is not able to connect to the cRIO after it disconnects. We tried pinging the cRIO from a different computer, but that also failed.
After disconnecting, the cRIO sends error messages to the serial port while trying to open a new TCP connection. It reports an error 56 (time-out error) 3 or 4 times (for a total duration of 15 or 20 seconds) and then reports an error 42 (generic error) at least 10 times per second for 18 seconds, and then switches back to 15 seconds of timeouts, and so on. When getting error 42, it ALWAYS gets it for 18 seconds straight. It usually gets error 56 for 15 seconds (3 timeouts) but sometimes for 20 seconds (4 timeouts).
When the cRIO disconnects, it can't be contacted by any computer through the ethernet port, yet the link lights still show that it is connected. If its connected directly, both the green and orange link lights on the cRIO light up, but when it is connected through the 10 Mb hub, only the orange link light lights up, but the hub shows that the cRIO is connected to it. In spite of this, it is still impossible to ping the cRIO in either scenario.
It is possible that, in addition to what computer the cRIO is connected to, the errors could be related to whether the cRIO has a direct connection to a computer or if it is connected through a hub. Today, we have only managed to get errors when the cRIO is directly connected to a laptop (one error after 1.5 minutes, one after 10 minutes, one after 7 minutes, etc.) There were no disconnects when the cRIO was connected to a 10 Mbps hub for more than half an hour.
Do any of those symptoms give you clues about what is happening?
Thanks!

Using fifos or indicators / varibles on cRio.

I'm currently working on the classical "remote, non-distributed measurement of voltages using the 9205 module" application. I was just wondering if I need at all to use fifos to transfer data from the fpga to the host computer on the cRio-9004. I did start out using a FIFO which I wrote to in the FPGA vi and then read it in a host vi. However extracting the array of data from the fifo using a for-loop seems to be a bit unstable with the values not always being transferred. I'm also a bit uneasy using buffers for a realtime sampling application when the language is so highlevel. So my question is:
Can I insert all my measurement data into an array and then read from the host VI using either indicators or variables, or will I run into throughput problems ?
I'm planning on using all of the 32 channels (at 16 bits) on the 9205 at a sampling frequency of 50 Hz - 200 Hz, plus some additional inputs.
Thanks,
Kevin

Hi Kevin,
You can achieve throughput rates an order of magnitude faster if you use the DMA FIFO transfer method versus front panel arrays. You will also have the benefit of DMA FIFOs taking up *significantly* less space on the FPGA than front panel arrays. Depending on what else your application is doing, you may be able to still do everything you need to through the front panel data transfer, but I highly recommend using the FIFO instead. If you're worried about data loss, just monitor the Full? output of the FIFO Write function on the FPGA to determine if any data is being lost.
FYI, we have a separate board for cRIO questions - this board is meant for the LabVIEW Embedded Development and LabVIEW Embedded For Blackfin Processors modules.
Cheers,
Matt Pollock
National Instruments

CRIO DMA FIFO transfer Issue-Voltage not coming to correct channels

Hi All,
Using crio 9073 and NI 9205, I am transferring Data (Channel data type = FXP, Word length 37 bits, 16 bits and FIFO also same data type) from FPGA DMA (Requested No of elements configured in FPGA is 16383) To RT DMA (Requested number of elements in 32744)
FPGA notes:
Total channels =16 (Differential mode)
Loop time of FPGA =20 ms (Per read 20 samples from each channel, so 320 samples per iteration)
RT notes:
SCTL=running at 10 ms where DMA transfer happening do that check remaining elements and then do DMA as well.
Issue:
When I run the code in above scenario, whatever different voltages given to 4 channels (loop backed 9263 to 9205, fpga interactive mode and only giving 4 channels voltages now just for testing) and i do DMA in RT side, decimate the 320 data and i found Channel 0 voltage given in FPGA is not coming in 0 index of the decimated array in RT DMA read data, instead Channel 0 voltage is coming in Index 7 of the RT DMA read data. Channel 1 coming at index 8...vice versa… Seems, some data shifting happening.
But in FPGA i could see correct differential voltage coming to correct channels (Ch 0 is 1.4 V ,FPGA indicator shows me correct voltage at index 0 a 1.4 and vice versa)..
Please suggest me why this is happening and what is best way i can get correct channel voltage data in RT based on my above conditions.

This is how I do where I need to only measure continuos analog values through FIFO. I don't use calibrated analog channel. I use raw analog channel and do calibration in host VI. I have attached screenshot of my code. I put 123456789 check sequence in build array function in FPGA VI.
If I want to read 2000 samples then I keep FIFO 4000 at host side.
I keep sample count in multiple of no. of channel. In my code build array has 3 element so I read 3*X. where X number of sample required per channel.
If you don't understand from code let me know.
PBP (CLAD)
Labview 6.1 - 2014
KUDOS ARE WELCOMED.
If your problem get solved then mark as solution.
Attachments:
FPGA VI.jpg ‏205 KB
FPGA 2.png ‏92 KB
Host VI.jpg ‏168 KB

Slowdown of FIFOs when performing multiple cRIO simulations - are FIFOs not reentrant?

I am simulating multiple cRIO chassis on a single multi-core machine, and have come across a problem with the FPGA FIFOs. A single simulation works fine, but when I have several simulations running in parallel, the FIFOs are considerably slower. I've put together a very simple example that demonstrates this, see attached. It seems like the FIFO is not re-entrant. Is there a way to change this behavior? My goal is to have a large number of simulations running, but I am currently limited to just 2 or 3 due to this FIFO slowdown. Any help would be appreciated. Thanks.
Attachments:
cRIO_Simulation.zip ‏249 KB

Hi Chris,
Thanks for taking the time to make an example project that clearly shows the problem you are seeing. When running on single mode, I see that the delay stays at around 30 ticks. When the Main vi is run on "Multi", I see a spike at the beginning, followed by a return to the delay levels we see for just one DMA FIFO. Because I was curious, I changed the delay in the FIFO_Read subVI to various ms values to see if it affected the average delay.
Here were my results:
Wait function (ms), Average delay (ticks), Multi spike (ticks)
1000, 50, 2000
500, 30, 2200
200, 20, 1200-2300
100, 10, 1500
Is this the performance that you are seeing as well? I noted that at some points my CPU utilization would spike to 40%. It seems like after the initial spike, the simulated Multi-target DMA FIFOs are able to run at a speed similar to a single target. Also, what version of LabVIEW/RT/FPGA do you have installed?
Joey S.
Software Product Manager
National Instruments

Simultaneous I/O with DMA FIFO channels on cRio

Hy everybody,
I work on a CompactRio 9014, with NI 9263 for analog output and NI 9215 for analog input.
I want to do simultaneous acquisition and generation using DMA channels: one on the first channel for the input and the second on the second channel for the output.
I have already read the example CompactRio Simultaneous AI and AO streaming But, if in this example the Analog input is done by a DMA FIFO, the output is done using the FPGA host interface read/write node (register I/O).
In my case I try to use two DMA channels, one for transfering the input datas and the second to transmit the output datas from the RT vi to the fpga VI.
So I have configure two FIFOs, both of size of about 4000. My sampling rate (for input and output) at the level of the fpga is 20KHz. I want to output blocks of size 2000 and simultaneous read something that is directly linked to my output. The problem, (I suppose) is that I have to wait on the Invoke Node (wich read block from the Input FIFO) that the reading of the block is completed. In my application, things works well at the beginning but after some seconds the output become instable.
I think the way I program my simultaneous analog I/O is not correct, but I don't see the right way to do that with two DMA channels. I have attached my RT VI and my FPGA VI. (the probleme of I/O is in the case "faulse" in the Room_measurements VI)
I hope somebody can help me.
Thanks in advance for your answers
Attachments:
Room_measurement_RT.vi ‏339 KB
Room_measurement_FPGA.vi ‏566 KB

Hello,
I now try to separate in two timed loops the input and the output. Each of the loops run at 100ms. The first loop (generation loop) must generate a sinus during 15 seconds(So the loop must run 150 times because dt is 100ms). The second loop (input), must record an input during 30 seconds. I am also not sure if the timeouts parameters of the FIFO read/write are correct.
I think this way (see the jpg) is better. But I still have several problems:
When I launch my VI, it works at the beginning but stops after some seconds (in fact I loose the connexion)
Also, if I stop the output loop before that the input stops, the VI also stops.
I hope somebody can help me
I attache my last_VIs
Attachments:
testAOAI1.vi ‏388 KB
Room_measurement_FPGA1.vi ‏566 KB

FPGA couldn't stack the data on FIFO working on cRIO-9082 and NI 9223 module

Hi all !
I made below logic working on FPGA ( chassis : cRIO 9082 / Analog input module : NI 9223 )
* These logic is for analyzing automotive engine combustion.
As title, it ain't work well.
Is there a basic mistake or any problem...?!
That makes me crazy.
Thanks for reading it anyway!

Sorry for the grammar
Any signal from FPGA is not transferred to RT.
Building process has no problem and logic seems to be okay..........
No error message!

Problem in Stock Transfer

Problem of Stock Tranfer :
Branches not make any STO for transferring any faulty material to Mahape, Because some material which are physically hold to branches not show in SAP Stock
Some material are dispatch from one branch to other branch, branch to Franchisee engineer how to maintain track threw SAP?
While making entries for PR & PO Or Making Document No(Storage location to storege location transfer ), I want to check matterial avelability for required plant, is it possible viweing the qunitity at time of entering PR.
After making I & C Confirmation and Techo , Billing Department not showing this data or showing partially process

Hello Tahir,
System's behaviour on FIFO is slightly change in case of inventory transfer. System does'nt keep any connection in physical FIFO (Serialized items) and FIFO cost in this case, as if one item first has been taken at USD 100 and then at USD 120, when you will transfer the stock and you choose 2nd serialized item which was taken at USD 120, system will pick the cost of USD 100 as of 1st item's cost because system creates layers for cost price and open quantities and at the time of inventory transfer, system only considers the first open layer of cost of the issuing warehouse. But all of this happens if your G/L determination is based on warehouse or item level. In case G/L determination is based on Item Group, your FIFO will work as per your requirements.
Regards,
Siddiq

Automatic BOM price roll-ups

My question is whether there is a user-friendly way of updating BOM prices in a volatile component environment. I think the answer is no, and that I will need to create a custom program to do so. The details...
We have several customers which manufacture fairly complex products, involving multiple levels of BOMs. Because of the volatility of component prices, and for tax purposes, FIFO costing is utilized. Thus, component costs will be changing on a daily basis. While I understand that the actual postings for a Production Order (PdO) will use the correct costs at the time of issue and FG receipt based on the item's costing method, these companies need to have reasonably accurate rollup costs in order to manage their selling prices. These rollup prices would be considered "reference" values, and it's understood that actual production costs would vary.
I've read dozens of posts and viewed an expert session on maintaining rolled BOM costs:
[https://websmp109.sap-ag.de/~sapidb/011000358700000185812008E/LOG_CW07_How_to_update.wrf]. If I've properly understood and consolidated the information, maintaining prices must be done manually or with the Update Parent Item Prices Globally function. Manual updates would be incredibly time consuming, and frankly, unacceptable. The UPIPG function will yield correct results only if it is performed from the lowest level subassembly BOM's first and finishing with the top-level finished goods. As far as I know, SBO has no "low-level code" in the item master to indicate the lowest BOM level in which it appears. Therefore, using the UPIPG function would still be a manual process and there is insufficient information to guide a user through the correct sequence.
The only solution I can see would involve creating an external program, which could be run periodically (e.g., nightly or on-demand). The output of this program would be an updated price list for all items, reflecting current costs. The program would first dynamically create a temporary table containing each item and its low-level code. Then, it would explode and cost BOMs starting from the lowest level, and progressing up the levels. Each higher level would use the newly-updated prices for the lower levels. The only SBO table updated would be the price list.
I've already scoped and prototyped this program, but wanted to check if there are other alternatives. Any feedback would be much appreciated.
Dave

Thanks for considering my question, Gordon.
I pretty much finished the program and initial tests are looking good. In case you're interested, the following is how I approached the problem.
The custom program is an external (DI-API) VB.net program, written as a console application (ie, no UI, command-line startup with parameters, can be initiated via Windows Scheduler). I added a UDF to the PriceList table, and the program updates only those price lists with a value in the UDF. The UDF value is a comma-separated list of warehouses whose inventory should be used to formulate the "current cost". For each PriceList, there are two passes. The first pass processes only BUY items, and computes a "current cost", depending on the cost method and whether costing is global or by warehouse. For FIFO items, an average FIFO cost is calculated across the designated warehouses. For Moving Average, a weighted average of the Moving Averages is determined. For standard cost items, the standard costs are averaged. The PriceList is updated to reflect this "current cost" (which is only a reference value). The second pass processes only MAKE items. Rather than updating a static low-level code each time, I simply flatten each BOM down to it's BUY or non-inventory parts, and use the newly-updated prices for the BUY items. Each make item's price is updated in the PriceList, if there's been a change. A bit of recursive programming made the BOM explosion fairly easy.
The result is one (or more) PriceLists that reflect an averaged cost for non-make items, and essentially a BOM rollup cost using the updated component costs. We'll be running it nightly, which should provide fairly good reference values. I'm still hoping that SAP will, at some point, add some kind of automated BOM rollup functionality that responds to changing component costs.
Dave

I want to check all functions of PCI 6534.I have read the user manual..I have some memory related questions.Please help me for that.

I want to check all functions of PCI 6534.I have read the user manual..I have some memory related questions.Please help me for that.
1.)If i am using the continuous output mode.and the size of generated data is less than 32 MB.If i want to preload the memory,what should i do?I want that first of all i load all my data to onboard memory & then i want to make start the transfer between 6534 & peripheral.Is it possible?As per me it should be.Plz tell me how should i do this?I think that in normal procedure the transfer between 6534-peripheral & outputting data from pc buffer to onboard memory works parallely.But i don't want this.Is it poss
ible?
(2).Similarly in finite input operation(pattern I/O) is it possible to preload the memory and then i read it?Because i think that the PC memory will be loaded automatically when 6534 acquires the data and then when we use DIO read vi the pc buffer data will be transferred to application buffer.If this is true,i do not want this.Is it possible?
(3) One more question is there if i am using normal operation onboard memory will be used bydefault right?Now if i want to use DMA and if i have data of 512 bytes to acquire.How will it work and how should i do it?Please tell me the sequence of operations.As per my knowledge in normal DMA operation we have 32 Bytes FIFO is there so after acquisition of 32 bytes only i can read it.How it will known to me that 32 bytes acquisition is complete?Next,If i want to acquire each byte separately using DMA interrupts what should i do?Provide me the name of sourse from which i can get details about onboard memory & DMA process of 6534 specifically
(4).In 6534 pattern Input mode,if i want to but only 10 bits of data.and i don't want to waste any data line what should i do?

Hi Vishal,
I'll try to answer your questions as best I can.
1) It is definitely possible to preload data to the 32MB memory (per group) and start the acquisition after you have preloaded the memory. There are example programs on ni.com/support under Example Code for pattern generation and the 6534 that demonstrate which functions to use for this. Also, if your PC memory buffer is less than 32MB, it will automatically be loaded to the card. If you are in continuous mode however, you can choose to loop using the on-board memory or you can constantly be reading the PC memory buffer as you update it with your application environment.
2) Yes, your data will automatically be loaded into the card's onboard memory. It will however be transferred as quickly as possible to the DMA FIFO on the card and then transferred to the PC memory buffer through DMA. It is not going to wait until the whole onboard memory is filled before it transfers. It will transfer throughout the acquisition process.
3) Vishal, searching the example programs will give you many of the details of programming this type of application. I don't know you application software so I can't give you the exact functions but it is easiest to look at the examples on the net (or the shipping examples with your software). Now if you are acquiring 512 bytes of data, you will start to fill your onboard memory and at the same time, data will be sent to the DMA FIFO. When the FIFO is ready to send data to the PC memory buffer, it will (the exact algorithm is dependent on many things regarding how large the DMA packet is etc.).
4) If I understand you correctly, you want to know if you waste the other 6 bits if you only need to acquire on 10 lines. The answer to this is Yes. Although you are only acquiring 10 bits, it is acquired as a complete word (16bits) and packed and sent using DMA. You application software (NI-DAQ driver) will filter out the last 6 bits of non-data.
Hope that answers your questions. Once again, the example code on the NI site is a great place to start this type of project. Have a good day.
Ron

CRIO; To FIFO or no to FIFO?

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