DDS Compiler (Xilinx Coregen IP) maximum achievable clock rate

Question

Hi,
I am using labview FPGA2011 and FlexRIO 7965R (i.e. Virtex5 SX95T). I have compiled a sinusoid generater using the built in Xilinx Coregen IP named 'DDS Compiler'. The output of DDS Compiler is sent to the host VI using DMA FIFO. My SCTL runs at 346MHz, as the largest clock that can be provided is 346.666MHz. The code according to DDS Compiler data sheet (DS558) with the configuration settings that i have used, should burn at 450MHz (mentioned in cloumn 4  of Table8 on page 28). But my code gives a maximum achievable clock rate of 350.63MHz. I have attached my code and images of the compilation results. Can somebody check and tell me why am i not getting the 450MHz rate? Is there any limitation on the clock rate due to the VI scoped or DMA FIFOs?
Thanks
Attachments:
DDS Compiler.zip ‏858 KB
images.zip ‏53 KB

Answer 1

Hi Sandee, 
What are you planning on doing with this sine wave?  Are you using a FlexRIO Adapater Module(FAM)?  
The reason you can't get anything higher than 346.66MHz is because the clock that is being generated from is a 40 MHz clock.  Once you multiply it up that high, the accuracy of the frequency is not reliable.  
The beauty of the FlexRIO is that you are able to bring in external clocks with several of our FAMs.  These external clocks are piped directly to the FPGA.  On top of that, if you're using the 6587 FAM, for example, you're able to generate up to a 500 MHz clock on the FAM, and provide that to the FPGA.  
To do that, you first add your adapter module to the project
Right click on your fpga target -> select new FPGA Base clock - > IO Module clock 0 from the drop down.  
Then specify your frequency to be 450 or 500, whatever you want it to be. 
Then on your block diagram, you'll provide your single cycle timed loop with the IO Module Clock 0 as the source. 
I'm going to compile it now and I'll update with the results. 
National Instruments
FlexRIO & R-Series Product Support Engineer