Designing digital filter for analog output

Hi all,
Iam working on pci-6723 NIDAQMX 7.3 LABVIEW 7.1 ENVIRONMENT.I have designed 16 channel data acquisition system.in order to supress glitches in the analog output signal ,which filter i have to adopt to the analog output generation. since i dont want to design hardware low pass filter , if i adopted digital filter will it improve the output signal performance ,kindly suggest me.with some example.
Regards
labview boy

Hello,
If you are talking about a software digital filter with the program that is producing the analog output, that will have no affect on an analog output signal. The glitching comes from the digital to analog converter (DAC). Check out this knowledge base article:
http://digital.ni.com/public.nsf/allkb/3BB2D5D837F6C9FE86256EAC007C123B
Really, your only solution is hardware.
If you are acquiring this signal on another data acquisition system and you want to remove the glitches from what you are seeing, you could use software filtering there.
-Alan A.

Similar Messages

  • Use soundcard for analog output

    Is it possible to use soundcard for analog output with LabView6?

    nicke wrote:
    > Is it possible to use soundcard for analog output with LabView6?
    Have a look in the examples under Hardware Input and Output|Sound (LV6.1)
    Dunno where it is under 6i, but the files are there.
    Impressed the crap out of some Fortran hackers by showing them how
    easy I could turn my laptop into a spectrum analyser.
    Remove "spamkill." when replying to this message

  • Digital trigger for analog scan

    I need to synchronize the start of several measurements with a trigger. I am using a NI 4472 input card and PCI-6731 output card. I need to trigger an analog scan on the 4472, a voltage output from the 6731, and trigger a dmm to start scanning with a digital output from the 6731.

    To trigger acquisition on the 4472 from a DIO line on a 6731, you would need to follow recommendations similar to Sal's. You could route the DIO line to a RTSI line on the PXI backplane, and then set up the 4472 to trigger acquisition off that RTSI line. You could also use an external connection and wire the DIO line to the "External Trigger" input on the 4472, and configure it to trigger off that signal. Probably the most important thing for you to do is make sure that everything that you want to trigger off that DIO line is setup and waiting for it before the trigger occurs.
    You can also use the example finder to find examples that will work with each individual device. In the bottom left-hand corner of the LabVIEW example finder, there is a button that you
    can click on to select or add the different pieces of hardware you want examples for. After you have configured that correctly, if you limit results to that hardware (check box), the only examples that you will see will be work with that piece of hardware. There are numerous examples of triggering on a digital line for the 4472. Hopefully this get's you moving. Good luck!
    Logan S.

  • How to structure the DMA buffer for PXie 6341 DAQ card for analog output with different frequencies on each channel

    I'm using the MHDDK for analog out/in with the PXIe 6341 DAQ card.
    The examples, e.g. aoex5, show a single Timer  (outTimerHelper::loadUI method), but the example shows DMA data loaded with the same vector size.
    There is a comment in the outTimerHelper:rogramUpdateCount call which implies that different buffer sizes per channel can be used.
       (the comment is: Switching between different buffer sizes will not be used)
    Does anyone know what the format of the DMA buffer should be for data for multiple channels with different frequencies ?
    For example, say we want a0 with a 1Khz Sine wave and a1 with a 1.5Khz sine wave.  What does the DMA buffer look like ?
    With the same frequency for each channel, the data is interleaved, e.g.  (ao0#0, ao1#0; ao0#1, ao1#1, ...), but when the frequencies for each channel is different, what does the buffer look like ?

    Hello Kenstern,
    The data is always interleaved because each card only has a single timing engine for each subsystem.
    For AO you must specify the number of samples that AO will output. You also specify the number of channels. Because there is only one timing engine for AO, each AO will channel will get updated at the same time tick of the update clock. The data will be arranged interleaved exactly as the example shows because each AO channel needs data to output at each tick of the update clock. The data itself can change based on the frequency you want to output.
    kenstern wrote:
    For example, say we want a0 with a 1Khz Sine wave and a1 with a 1.5Khz sine wave.  What does the DMA buffer look like ?
    With the same frequency for each channel, the data is interleaved, e.g.  (ao0#0, ao1#0; ao0#1, ao1#1, ...), but when the frequencies for each channel is different, what does the buffer look like ?
    In your example, you need to come up with an update rate that works for both waveforms (1 KHz and 1.5 KHz sine waves). To get a good representation of a sine wave, you need to update more than 10x as fast as your fastest frequency...I would recommend 100x if possible.
    Update Frequency: 150 KHz
    Channels: 2
    Then you create buffers that include full cycles of each waveform you want to output based on the update frequency. These buffers must also be the same size.
    Buffer 1: Contains data for the 1 KHz sine wave, 300 points, 2 sine wave cycles
    Buffer 2: Contains data for the 1.5 KHz sine wave, 300 points, 3 sine wave cycles
    You then interleave them as before. When the data is run through the ADC, they are outputting different sine waves even though the AO channels are updating at the same rate.

  • PCI Card for Analog output in the range of 10mv

    dear ni,
                    I want to know about the PCI card that can be generate analog output in the range of maximum 10mv. i  am going to use for caliberation of loadcell, strain gauges devices.
    could you tell me on which PCI card will support this type of application.
    Regards,
    Balaji DP

    Try:  http://www.ni.com/dataacquisition/
    These have analog output voltages < 10V:   http://sine.ni.com/nifn/cds/view/main/p/sn/n12:7604,n3:7853/lang/en/nid/1036/ap/daq
    You need something with a high bit count to get good resolution at 10 mV, such as the PCI-6010 which has a 16 bit D/A.   
    Here are the minimum voltage specs for the 6010:
    Minimum Voltage Range
    -0.2..0.2 V
          Range Accuracy
    283 µV
          Range Sensitivity
    6.4 µV
    Message Edited by vt92 on 11-18-2009 07:56 AM
    "There is a God shaped vacuum in the heart of every man which cannot be filled by any created thing, but only by God, the Creator, made known through Jesus." - Blaise Pascal

  • How to reset buffer pointer for analog output generation?

    I am doing a finite analog output generation on a USB-6216
    Sequence of events:
    DAQmx Create Task
    DAQmx Timing (finite samples, 1000Hz)
    Use DAQmx timing property SampQuantamples per channel to set buffer size
    Write buffer with DAQmx Write
    Repeat
      DAQmx Start Task
      DAQmx Wait until done
      DAQmx Stop Task
    Until finished
    DAQmx Clear Task
    I get a full waveform output on the first iteration of the loop. On subsequent iterations I get only a small section of the waveform, but no error. It seems that it is regenerating the waveform, because when I switch off regeneration I get an error at Start Task, but before it can regenerate all the data Wait Until Done.vi decides that the generation is done and exits, stopping the generation.
    I have done this with a PCI device and it works fine; every call to Start Task generates the whole waveform again.
    OK, so it looks like after every waveform generation completes I need to reset the pointer to the start of the buffer, so that the Wait Until Done vi does not think the generation is done. Or - maybe there is a way to reset the "Generation Done" state?
    I'm sure there's an easy way to do this....?

    Hi CDancer,
    Many thanks for contacting National Instruments. If I can start by giving some general advice, it would be well worth posting your actual VI. This helps others on this forum in helping you with your application. 
    From the sounds of things, you want to do continuous analog output generation. I have had a look at the examples that come with LabVIEW and I think you should look at the one below.
    I would have a look at some of the DAQmx examples that come installed with LabVIEW. The following example would be particularly relevant I feel
    Cont  Gen Voltage Wfm-Int Clk-non Regeneration.vi 
    Please let me know how you get on.
    Many thanks,
    Andrew McLennan
    Applications Engineer
    National Instruments

  • Configure digital filter for external clock

    I am trying to use a digital filter on my PXI-6602 card and I can't get it to configure for an external clock. It keeps telling me the numbers don't match up but I don't see the logic to the numbers it supports. Here is the error I got for a time base of 100 Hz and a min pulse width of 1/(100 / 2) based on the period of 2 clock cycles.
     Desired Minimum Pulse Width could not be produced.
    Minimum Pulse Width is affected by the Digital Filter Timebase Source and the Digital Filter Timebase Rate. To see how these two property settings can affect the Minimum Pulse Width, refer to product documentation for more details.
    Property: CI.CountEdges.DigFltr.TimebaseSrc
    Requested Value: /PXI1Slot2/PFI36
    Property: CI.CountEdges.DigFltr.TimebaseRate
    Requested Value:  100.000000
    Property: CI.CountEdges.DigFltr.MinPulseWidth
    Requested Value:  20.0e-3
    Supported Values:  80.0e-3 to  171.798692e6
    Task Name: _unnamedTask<49>
    I know my math is off since the filter uses the leading edge of the pulse but 0.08 seconds is 12.5 Hz and I don't get it. Other frequencies produce different but also odd (to me) numbers.
    Attached is a copy of my VI
    Attachments:
    External Clock for Filter.jpg ‏131 KB

    Digital filtering ensures that a high pulse is high for at least a certain time (minimum pulse width) in microseconds.  This is to ensure that a fluke noise signal does not count as a high pulse.  It also ensures that a voltage overshoot to the high value does not register more than one high pulse as it settles in to the value.
    The specifications of the digital filtering is outline on page 3-1 to 3-3 of the 660x User Manual, found here. It specifies on page 3-3 that there are five different settings for the digital filter minimum pulse width:
    5 µs 
    1 µs 
    500 ns 
    100 ns 
    Or, programmable with a custom tfltrclk (period in seconds of Filter Clock).  However, when using tfltrclk, minimum pulse width needs to equal to 2*tfltrclk.  Your current setup has the minimum pulse width set up for minimum pulse width = 1/(tfltrclck/2) = 2/tfltrclck rather that 2*tflrclk.
    I think you already knew all of this.  However, the Filter Clock does not equal the Filter Clock Timebase.
    If we look on page 3-3 in the manual we seed that Filter clock is actually 1/4th the speed of the Filter Clock Timebase.  
    Therefore, in your setup:
    Filter Timebase Rate = 100Hz
    Filter Clock Rate= 1/4th *100 Hz = 25Hz
    Filter Clock Period = 1/25Hz = 0.04 seconds
    2*Filter Clock Period = Minimum Pulse Width = 2*0.04=0.08 seconds.
    Which is the minimum value it was suggesting.  This will always be four times as large as what you were guessing before.
    Eric S.
    AE Specialist | Global Support
    National Instruments

  • Synchronize two PCI Board for Analoge Output

    Hi All
    Has anyone a good example for synchronizing two MIO Boards over RTSI cable.
    I found a lot examples to analoge input but nothing about analoge output.
    Thanks

    Hi Reto.
    I posted to this once, but looks like it didn't make it. I checked the examples, and Ir eally didn't see anything that did what you wanted over the RTSI bus, so I made one. Check it out.
    Mark
    Attachments:
    RTSI_AO.vi ‏95 KB

  • Digital triggering for analog acquisition on PCI-6024

    I would like to initiate an analog input scan when a digital line goes low using a PCI-6024 board. I connected the digital line to TRIG, and the analog line to AIN0. I tried using "Acquire N - Multi-Digital Trig.vi"...it almost works. It acquires a scan, but it may (randomly) start at either the rising or falling edge of the trigger, regardless of the rising/falling trigger edge setting. How do I get it to only acquire data on a falling edge?

    Dear Dave -- If you set up your task using MAX, you can specify whether you need to start acquiring at the rising or the falling edge. Using this task in your experiment should effectively take care of the issue.
    You can do the same from LabVIEW as well using the DAQmx Trigger VI and set the acquisition to begin at the rising or falling edge as you may choose it to be.
    HOpe this helps = VNIU

  • How to combine the analog input and analog output vi's

    Hi !
    I have a perfectly running triggered analog input acquisition vi. I have a seperate vi for analog output that's running perfectly too. Can someone tell me how to combine these two operations so that I could get a vi that does simulataneous AI and AO without missing triggers. I have tried all the different kinds of configurations suggested by NI support but nothing seems to work. Can someone help ?
    thanks,
    Shiva
    Attachments:
    dac_good.vi ‏77 KB
    adc_good_fw.vi ‏124 KB

    Shiva;
    I'm attaching a good Application Notes that shows how to synchronize multiple DAQ tasks, in Labview.
    Hope this helps.
    Filipe
    Attachments:
    Advanced_Sync_Techniques_for_DAQ.zip ‏166 KB

  • Breakoutbo​x for Digital and Analog Output

    Hallo everybody
    i need  to design a breakout box with BNC and SMD connectors for Digital and Analog output (the DAQ cards we use are  PXI-6723 for analog and PXI 6259 mostly for the digital an fast AO Channels) I am looking for tutorials and info material for that. On what I have to pay attention what would be a good circuit diagramm design and so on.
    Maybe you could give me some tips where I can find good Material about that.
    Sebastian

    Hello Sebastian
    first of all I'll need some more information about your intention. What exactly are you going to do? Do you want to connect, or divide signals? (Which signals?)
    Maybe if you have a look in the manuals of the cards, you'll get closer to this. Here you can find out the pin assignment of the cards.
    Manuals and specification:
    PXI-6723:
    http://www.ni.com/pdf/manuals/370822c.pdf
    http://www.ni.com/pdf/products/us/04-3513-301-101-​DLR.pdf
    PXI-6259
    http://www.ni.com/pdf/products/us/044063301101dlr.​pdf
    http://www.ni.com/pdf/manuals/371291h.pdf
    Regarding
    Gregor Allexi

  • Digital Filter Design Toolkit for LabVIEW 8.0

     I need Digital Filter Design Toolkit for LabVIEW 8.0 and I cannot find it on the site.Where can I get it from?

    Contact your local NI representative. He might just sent you one.

  • Combine Analog outputs for higher current drive

    I'm using a cRIO 9263 analog output module.  The current output specification is 1 mA.  If I need 1.2 mA of current, can I use two outputs in parallel?
    SteveA
    CLD
    FPGA/RT/PDA/TP/DSC

    I am not familiar with that device, but, in general when paralleling voltage output devices which were not specifically designed to be paralleled you need to include some ballast resistors. They allow for slight differences in the output voltages of the two (or more) devices and promote current sharing.
    Put one resistor in series with each output. Connect the other ends of the resistors together and connect this to the load. The value of the resistors depends on the amount of current, the voltage difference between the two outputs when given the same digital code, how much voltage drop in the resistors can be allowed, and perhaps other factors such as how fast the output must change.
    I can help with the calculations if you are not familiar with them, but I will need more information about the voltages and loads.
    Lynn

  • Digital audio adapter for analog phones

    I would like to use the Toslink output and use a digital-to-analog headphone amp for my studio-quality headphones. I can find a digital to analog converter for quite a large sum of money - for me - at around $500.
    1. Does anybody have any ideas for a digital to analog converter that won't break the bank?
    2. Would I be better using USB as opposed to the Toslink/S=PDIF headphone output?
    3. If USB is the better way to go, does anybody have any recommendations for a brand?
    Thank you

    Hi cube60
    I'll let you have my old Pioneer Stereo Receiver for a $100, it supports Digital (Toslink) input and you can plug your headphones into it.
    Not really, but be aware that you may already have or can find a real nice used receiver that supports digital input for way less than that amp. your looking at.
    Dennis

  • How to design a stable IIR-Filter for FPGA?

    Hi, I´m new to Labview for FPGA and currently trying to design a lowpass-filter (for a digital mixer, more or less). It should work with a sample-frequency of 200kHz, a passband edge frequency of 3Hz and a stopband edge frequency of 8Hz. An FIR-filter would have a too large order to be implemented, an IIR one seems more practicable. For the design of the filter I'm using the digital filter design toolkit, refering to its manual and the casestudy with analyzing, modeling, simulating and generating a fixed-point filter. Now, I have problems to get a stable filter. While the manual states to adjust the coefficents by trial and error, the designed filter never matches the floating-point reference. Does anyone have experience in creating such filters? Or a hint, how to optimize the coefficient finding process?
    Thanks in advance!
    thilo

    LabVIEW FPGA 8.20 does include a Butterworth filter function (1st, 2nd and 4th order) in the FPGA palette. You can configure it directly using a dialog on your FPGA diagram. The cutoff may not be quite as sharp as you want but it could be an option for you to consider. Once you have configured the filter VI, you have the option of opening up the subVI with the code that is generated based on your filter parameters, which would allow you to further configure the code directly.
    I have attached the configuration dialog with the settings you specified.
    Message Edited by Christian L on 11-16-2006 09:27 AM
    Christian Loew, CLA
    Principal Systems Engineer, National Instruments
    Please tip your answer providers with kudos.
    Any attached Code is provided As Is. It has not been tested or validated as a product, for use in a deployed application or system,
    or for use in hazardous environments. You assume all risks for use of the Code and use of the Code is subject
    to the Sample Code License Terms which can be found at: http://ni.com/samplecodelicense
    Attachments:
    filterdialog.JPG ‏44 KB

Maybe you are looking for