Configure digital filter for external clock

Question

I am trying to use a digital filter on my PXI-6602 card and I can't get it to configure for an external clock. It keeps telling me the numbers don't match up but I don't see the logic to the numbers it supports. Here is the error I got for a time base of 100 Hz and a min pulse width of 1/(100 / 2) based on the period of 2 clock cycles.
 Desired Minimum Pulse Width could not be produced.
Minimum Pulse Width is affected by the Digital Filter Timebase Source and the Digital Filter Timebase Rate. To see how these two property settings can affect the Minimum Pulse Width, refer to product documentation for more details.
Property: CI.CountEdges.DigFltr.TimebaseSrc
Requested Value: /PXI1Slot2/PFI36
Property: CI.CountEdges.DigFltr.TimebaseRate
Requested Value:  100.000000
Property: CI.CountEdges.DigFltr.MinPulseWidth
Requested Value:  20.0e-3
Supported Values:  80.0e-3 to  171.798692e6
Task Name: _unnamedTask<49>
I know my math is off since the filter uses the leading edge of the pulse but 0.08 seconds is 12.5 Hz and I don't get it. Other frequencies produce different but also odd (to me) numbers.
Attached is a copy of my VI
Attachments:
External Clock for Filter.jpg ‏131 KB

Answer 1

Digital filtering ensures that a high pulse is high for at least a certain time (minimum pulse width) in microseconds.  This is to ensure that a fluke noise signal does not count as a high pulse.  It also ensures that a voltage overshoot to the high value does not register more than one high pulse as it settles in to the value.
The specifications of the digital filtering is outline on page 3-1 to 3-3 of the 660x User Manual, found here. It specifies on page 3-3 that there are five different settings for the digital filter minimum pulse width:
5 µs 
1 µs 
500 ns 
100 ns 
Or, programmable with a custom tfltrclk (period in seconds of Filter Clock).  However, when using tfltrclk, minimum pulse width needs to equal to 2*tfltrclk.  Your current setup has the minimum pulse width set up for minimum pulse width = 1/(tfltrclck/2) = 2/tfltrclck rather that 2*tflrclk.
I think you already knew all of this.  However, the Filter Clock does not equal the Filter Clock Timebase.
If we look on page 3-3 in the manual we seed that Filter clock is actually 1/4th the speed of the Filter Clock Timebase.  
Therefore, in your setup:
Filter Timebase Rate = 100Hz
Filter Clock Rate= 1/4th *100 Hz = 25Hz
Filter Clock Period = 1/25Hz = 0.04 seconds
2*Filter Clock Period = Minimum Pulse Width = 2*0.04=0.08 seconds.
Which is the minimum value it was suggesting.  This will always be four times as large as what you were guessing before.
Eric S.
AE Specialist | Global Support
National Instruments