Device supports sample clock input

I'm trying to find the best way to check if an NI device supports sample clock input. For example, I have a USB-6008 which does not support sample clock input. When I call DAQmxGetDevTerminals, I get "/Dev1/ai/StartTrigger, /Dev1/PFI0". For start trigger capability, I can call DAQmxGetDevAITrigUsage or look in the terminals string for "ai/StartTrigger". Should I search the string for "ai/SampleClock", or is there a function similar to DAQmxGetDevAITrigUsage?
Thank you,
CV

Hey CV,
From what I've seen, I don't know of a function similar to DAQmxGetDevAITrigUsage that works with the sample clock. It sounds like searching the terminal string may be your best bet for achieving the functionality you're looking for.

Similar Messages

Aggregate devices and sample clock sync

Hi All,
Finally got the 2.8 8 core Mac Pro and am wondering how easy it is to sync multiple interfaces with sample accuracy. Would word clock be the route to take ?
Has anyone done this with 2 devices from different manufacturers ?
Btw, no cpu spikes here. Everything runs smoothly.... however , everything is all Apple.
Cheers !!

Hi,
I just had a terrible time with a TC Konnekt 24D on brand new MacPro. Let down by really awful drivers but a lovely piece of kit otherwise. How do the m-audio drivers fare? I'll be using it with a Yamaha 01v96 v2 mixer, world clock delivered through the lightpipe itself but there is also a separate connection.
Do you have firewire conflicts say with a FW iSight or FW Printer/Scanner?
30/03/2008 09:08:20 kernel ential FireWire workloop deadlock!
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Use analog input as sample clock

Hi,
I have a PCI 6115 DAQ card. I currently perform an
analog acquisition on ai0, with an external clock on PFI7. But
sometimes, my clock signal is not high enough and the acquisition does
not occur. At some NI show, I heard a trick to solve this problem :
plug the clock on analog input (say ai1), the clock signal gets
amplified by the card internal amplifiers, and then route this
amplified signal to the sampling clock. This seems to be a wonderfull
solution, but I cannot find out to actually redirect the amplified ao1
to the sampling clock. Does someone know how to do it ?
Thanks a lot,
Jérôme Lodewyck

I tested the attached example on a simulated device so hopefully it will work on a real one without any kinks. You didn't specify your programming environment, so I'm assuming you're using LabVIEW. If not, hopefully you can translate to the appropriate ADE based on the picture of the block diagram.
In the example, I'm using an AO task to program the analog trigger as specified. This has two consequences. First, you won't be able to perform hardware timed AO while the AI acquisition is running. If this isn't acceptable, you'll need to try the second approach described in the next paragraph. Second, you'll have to wire the signal to PFI0 instead of an AI channel. With this configuration, the signal will be seen with a +/- 10V range and referenced to AI Gnd. Since the trigger DAC is an 8 bit comparator circuit for this board, you'll have ~80 mV of resolution. You didn't mention what the amplitude or DC offset (if any) of your signal is, but hopefully this resolution will suffice. You can use the level and hysteresis properties for the analog trigger to filter out noise in the analog signal or account for DC offset.
If the constraints listed above aren't to your liking, you can try to use a second AI channel as a trigger channel. This has some advantages and disadvantages. The disadvantages are that this requires you to use a trigger with your AI task and it also requires you to acquire another channel of data. You mentioned the trigger wasn't a problem so this can probably be taken care of with simple analog start trigger. The data can easily be thrown away, but depending on your sampling rates, it might require a lot of extra bus bandwidth or processing power when scaling the data. On the positive side, it doesn't require you to use up your AO channels needlessly and you can apply gain to the input signal in order to effectively increase the resolution of the trigger circuit. You can also apply a low pass filter and different terminal configuration if desired. The gain, coupling, terminal configuration, filtering, and coupling applied to the signal is controlled by the values used in the Create Channel VI and the Channel Property node. To create an example that does this, simply start with one of the shipping examples for an Analog Start trigger, change the trigger source to one of the AI channels instead of a PFI or APFI pin, and change the clock source to the AnalogComparisonEvent as shown in the attached example.
That should do it. Good luck with your application and post back if you have additional troubles.
Attachments:
AI - External Clock Using Analog Trigger Circuit.vi ‏81 KB
AI - External Clock Using Analog Trigger Circuit.JPG ‏60 KB

"External sample clock" and "Rate" for digital input acquisition

Dear all,
I want to acquire digital input (21 bits with external clock = 50 kHz) with a PCIe-6343 NI board. Using the DAQ assistant under Labview, I selected the advanced timing with the sample clock time parametrized as External. However, it is also possible to select the Rate of the acquisition. In my case, i want to get the data at the rising edge of the external clock signal, so at a frequency of 50 kHz. How can I do that ? I just need to put a Rate of 50 kHz ?
thanks for your help.
Cedric

Cedric,
dddsdsds wrote:
[...]In my case, i want to get the data at the rising edge of the external clock signal, so at a frequency of 50 kHz. How can I do that ?[...]
You answered your question already. If you want to use an external clock, you have to configure the timing source of your task to be external. In order of proper buffer configuration, you should enter 50kHz as rate in addition to the external configuration, but this will not influence the speed of the acquisition (since it is "clocked" externally!)
hope this helps,
Norbert
CEO: What exactly is stopping us from doing this?
Expert: Geometry
Marketing Manager: Just ignore it.

Is SMA clock input supported in Spartan3E FPGA driver?

Hi,
I am using Labview 8.6 FPGA module for Spartan3E board. Is SMA clock input supported in Spartan3E FPGA driver?
If I use SMA clock input, Labview reports error (OnboardClock tag missing) when I compile VI. If I use both of two, it reports too much clock resources used.
Anyone can help this? Thanks.
Bynan

The error message is:
Required tag was not found in the resource file.
Target name: FPGA Target (Dev1, Spartan-3E Starter Board)
Tag: OnboardClock

Using an internal sample clock with a digital input

I am using an encoder to measure angle and velocity. The example that I have started with is here. https://decibel.ni.com/content/docs/DOC-6834. The problem I am having is with the Sample clock, I get a timeout at the DAQmx read. If I remove the sample clock the VI runs fine, but I have no idea of my sample rate. Below is the the problem setup with the Sample clock inline.
Attachments:
encoder with timer.JPG ‏50 KB

Hi there, a couple suggestions: first , this is a post that it is suppose to be on the DAQ board. Second, you are not being clear about the error, try to include the error code, description and its location, is it coming out of the channel node or the timing VI? Also what hardware are you using?
Now, If you open the example called "Measure Angular Position.vi" from the NI example finder, drill the DAQmx Create Channel, you will see that you are missing a couple terminals for the task configuration, I wonder if this is part of the error.
Alejandro | Academic Program Engineer | National Instruments

Unable to use sample clock digital filter - PCI6602

I can't seem to get digital filtering of the sample clock to work on my PCI6602. I'm using DAQmx 7.4, with one of the counters configured for buffered-edge counting. Whenever I try to configure digital filtering on the sample clock (coming in on pfi10):
counterTask.Timing.SampleClockDigitalFilterEnable = true;
counterTask.Timing.SampleClockDigitalFilterMinimumPulseWidth = 0.000005;
I get the following error message when I start the task:
Additional information: Digital filtering is not available for the given terminal.
Device: Dev3
Property: NationalInstruments.DAQmx.Timing.SampleClockSource
Corresponding Value: /dev3/pfi10
Channel Name: phaseLockOscillator
Task Name: PhaseLock task
Status Code: -200772
I thought digital filtering was supported on all pfi inputs on the 6602 - so can anybody give me a hint as to what I'm doing wrong !?
Many thanks in advance,
Jony Hudson

I have the same problem with the PCI-6280., help me please!

Buffered event counting. Why can't I explicitly sequence generating the Sample Clock Pulse and reading the counters?

At irregular occasions I need to grab counts from several counters, and buffering the counts must be done simultaneously for all counters. I'm modeling my approach after zone.ni.com/devzone/cda/tut/p/id/5404 which someone kindly pointed out in an earlier thread. However, that example only uses one counter, and you can't test the synchronization with only one counter, so I am using two counters configured the same way, and they're wired to a single benchtop signal generator (for example at 300 kHz).
What I want to do, I can test in a loop with a somewhat random wait in it. I want to drive a hardware digital output line high for a few ms and then low again. The hardware line is physically connected to terminals for my timing vi's Sample Clock Source and so will cause them to buffer their counts for later reading. After I pulse this line, when I know new good buffered counts await me, I want to read both my counters. If their bufferings are simultaneous, then each counter will have counted the same number of additional counts since the last loop iteration, which I can check by subtracting the last value sitting in a shift register and then subtracting the two "additional counts" values and displaying this difference as "Diff". It should always be 0, or occasionally +1 followed immediately by -1, or else the reverse, because buffering and a count could happen practically at the same moment.
When I do this using a flat sequence to control the relative timing of these steps, so the read happens after the pulse, the counters often time out and everything dies. The lengths of time before, during, and after the pulse, and the timeout value for the read vi, and the size of the buffer and various other things, don't seem to change this, even if I make things so long I could do the counting myself holding a clipboard as my buffer. I've attached AfterPulse.vi to illustrate this. If I get 3 or 10 or so iterations before it dies, I observe Diff = 0; at least that much is good.
When I use two flat sequences running in parallel inside my test loop, one to control the pulse timing, and the other to read the counters and do things with their results, it seems to work. In fact, Diff is always 0 or very occasionally the +/- 1 sequence. But in this case there is nothing controlling the relative timing such that the counters only get read after the pulse fires, though the results seem to show that this is true. I think the reads should be indeterminate with respect to the pulses, which would be unreliable. I don't know why it's working and can't expect it to work in other environments, can I? Moreover, if I set some of the pulse timing numbers to 1 or 2 or 5 ms, timeouts start happening again, too. So I think I have a workaround that I don't understand, shouldn't work, and shouldn't be trusted. See SeparateSequence.vi for this one.
I also tried other versions of the well-defined, single sequence vi, moving the counter reads to different sequence frames so that they occur with the Sample Clock Source's rising edge, or while it is high, or with the falling edge, and they also often time out. I'll post these if anyone likes but can't post now due to the attachment limit.
Here's an odd, unexpected observation: I have to sequence the reads of the counters to occur before I use the results I read, or else many of the cycles of this combine a new count from one counter with the one-back count from the other counter, and Diff takes on values like the number of counts in a loop. I though the dataflow principle would dictate that current values would get used, but apparently not so. Sequencing the calculations to happen after the reads fixes this. Any idea why?
So, why am I not succeeding in taking proper control of the sequence of these events?
Thanks!!!
Attachments:
AfterPulse.vi ‏51 KB
InSeparateSequence.vi ‏49 KB

Kevin, thanks for all the work.
>Have you run with the little execution highlighting lightbulb on? -Yes. In versions of this where there is no enforced timing between the counter and the digital line, and there's a delay inserted before the digital line, it works. There are nearly simultaneous starts on two tracks. Execution proceeds directly along the task wire to the counter. Meanwhile, the execution along the task wire to the digital high gets delayed. Then, when the digital high fires, the counter completes its task, and execution proceeds downstream from the counter. Note, I do have to set the timeout on the counter longer, because the vi runs so slowly when it's painting its progress along the wires. If there is any timing relationship enforced between the counter and the digital transition, it doesn't work. It appears to me that to read a counter, you have to ask it for a result, then drive the line high, and then receive the result, and execution inside the counter has to be ongoing during the rising line edge.
>from what I remember, there isn't much to it. There really aren't many candidate places for trouble. A pulse is generated with DIO, then a single sample is read from each counter. -Yup, you got it. This should be trivial.
>A timeout means either that the pulse isn't generated or that the counter tasks don't receive it. - Or it could mean that the counter task must be in the middle of executing when the rising edge of the pulse arrives. Certainly the highlighted execution indicates that. Making a broken vi run by cutting the error wires that sequence the counter read relative to the pulse also seems to support that.
>Have you verified that the digital pulse happens using a scope? -Verified in some versions by running another loop watching a digital input, and lighting an indicator, or recording how many times the line goes high, etc. Also, in your vi, with highlighting, if I delete the error wire from the last digital output to the first counter to allow parallel execution, I see the counter execution start before the rising edge, and complete when the line high vi executes. Also, if I use separate loops to drive the line high and to read the counter, it works (see TwoLoops.vi or see the screenshot of the block diagram attached below so you don't need a LV box). I could go sign out a scope, but think it's obvious the line is pulsing given that all these things work.
>Wait! I think that's it! If I recall correctly, you're generating the digital pulse on port0/line0... On a 6259, the lines of port 0 are only for correlated DIO and do not map to PFI. -But I'm not using internal connections, I actually physically wired P0L1 (pin 66) to PFI0 (pin 73). It was port0/line1, by the way. And when running some of these vi's, I also physically jumper this connection to port0/line2 as an analog input to watch it. And, again, the pulse does cause the counter to operate, so it clearly connects - it just doesn't operate the way I think it is described operating.
For what it's worth, there's another mystery. Some of the docs seem to say that the pulse has to be applied to the counter gate terminal, rather than to the line associated with the sample clock source on the timing vi. I have tried combinations of counter gate and or sample clock source and concluded it seems like the sample clock source is the terminal that matters, and it's what I'm using lately, but for example the document I cited, "Buffered Event Counting", from last September, says "It uses both the source and gate of a counter for its operation. The active edges on the gate of a counter is used to latch the current count register value in a hardware register which is then transferred via Direct Memory Access...". I may go a round of trying those combinations with the latest vi's we've discussed.
Attachments:
NestedSequences.png ‏26 KB

Can I use a substitute for the Sample Clock?

I have three different analog inputs coming from one device (PCI-6221). Two inputs are running at the same sample rate while the third needs a faster sample rate and a trigger. I have these seperated as two seperate tasks but my problem is they both use the sample clock. Can I use a substitute for the sample clock on the third channel?
I am running LabVIEW 8.2 on Windows XP.
Thanks in advance for your help.
Ron Deavers, CLD

Hi programmindragon,
I understand you are trying to
configure your PCI-6221 to sample on multiple channels, while having
different rates and triggers for the channels. Unfortunately, you can
only configure one analog input task to run at once and all the channels in
the task must share the same configurations, including the sample clock
and trigger. This is due to the fact that all the channels are
multiplexed to a single amplifier and ADC on the device. Thus, you will
not be able to configure the two inputs at one rate and use a different
clock rate and trigger for the third input. Is it possible to sample at the
maximum rate on all channels and decimate the data that you don't need on the certain
channels, as well as share the same type of triggering? Hopefully you will be able to run your application with the same configuration across multiple channels, otherwise you may need multiple DAQ devices. Please let me know if you have any further questions related to this issue.
Regards,
Daniel S.
National Instruments

Using AI Sample Clock to Trigger Counter Samples

My basic question is: Is the ai\SampleClock signal only active while an analog input task is running?
The details are:
I have an X-series PCIe-6321 multifunction DAQ card. It is controlling a SCXI chassis and has a SCXI-1180 and SCXI-1302 so I can control analog inputs of the chassis as well as access the 4 counter on the card. My application requires that I use all 4 counters to measure a frequency input signal and synchronize the samples to the analog input signals. I have created 5 tasks, 1 for the AI and 1 for each counter.
I am using LabVIEW 8.6.1 with the latest NI-DAQ drivers on and 64-bit Vista OS
1. Are there any driver or hardware restrictions that would cause this solution not to work?
2. Can I use the ai\SampleClock as in input sample clock for each of the frequency tasks? If I do this will the sampling start be syncronized? I.e. if I start each of the frequency tasks first, will they wait until the AI task is started before they start sampling?
3. If that doesn't work, do I need to route the sample clock from the AI task to a PFI line (PFI1) and then use that as input to the frequency task sample clock?
I usually do option 3 when synchronizing two cards in PXI chassis and only use the software task start in stead of of synchronizing on a digital start, since the sample clock will control the samples anyway. I need to know if the same behaviour works with the scenario above.
Thanks,
Bob
Prolucid Technolgies Inc.
Solved!
Go to Solution.

Hi Bob,
I can confirm that the ai/SampleClock will only be active while the AI task is running. As far as the other questions go:
1. You'd have to provide more information about what you looking to do exactly, but there is no problem with routing the sample clock of the Analog Input task to be used with the Counters. I would read through the section of the X Series User Manual that discusses sample-clocked frequency measurements (starting on page 7-16) for some more information about what is actually going on during this configuration to make sure it suits your requirements.
The frequency of the signal to be measured should be at least twice as fast as the sample clock of your AI task.
2. You can indeed route the signal to all four tasks at the same time (you can refer to the Device Routes page in MAX to double-check routing restrictions). The sampling will be synchronized provided the four counters are started before the AI task, but the counters will be armed at different times unless you configure an Arm Start Trigger (see page 7-45 of the X Series User Manual). I would consider using the ai/StartTrigger if you wish to do this.
The effect of not arming the counters at the same time would be a different number of periods to average on each counter for the very first sample (assuming averaging is enabled). This might not be a big concern but I just wanted to point it out.
3. The routes are available internal to the board so external routing isn't necessary, you can just specify to use the AI Sample clock for the clock of each counter and the routes will be made for you. If you prefer to export the signal on a PFI line and route it back in on a different PFI line this option is also available to you but shouldn't be necessary.
I hope this helps you get started. I'd make sure to take a look at chapter 7 of the X Series User Manual if you get a chance since it describes how all of the counter configurations work in more detail. If you have any related questions don't hesitate to post back.
Best Regards,
John
Message Edited by John P on 12-01-2009 07:52 PM
John Passiak

NI 5772 acceptible external sample clock

Hello support forum,
Is it possible to use the NI 5772 adapter module with an external sample clock that does not have a constant frequency (it is still within the 400-800MHz range though), and is not always on?
An illustration of the clock signal may be more useful. Here is a link to a PDF containing a description of the instrument that is generating the clock signal. The plot of the clock signal is shown on page 7, it is the purple waveform (refered to as '(3) DAQ k-clock signals' in the text below the figures).
http://www.thorlabs.com/thorcat/22700/SL1310V1-10048-Manual.pdf
I've attached a screenshot of page 7 to this post in case the PDF is inconvienent.
Page 7 contains two figures. The top figure illustrates what I mean when I say the clock is not 'always on'.
The clock signal is supposed to be close to 500MHz, but it is not necessarily always that frequency. The frequency is dependent on the device. The device is a swept source laser. Each 'sweep' may result in a slightly different clock frequency, even within one sweep.
I can provide a lot more detail on my application if required.
Thank you for your help.
Solved!
Go to Solution.

The CLIP that we ship with the 5772 requires a persistent clock that maintains relatively stable frequency. If you need to use a 5772 with a variable frequency clock that is not persistent then you will need a custom CLIP. Depending on your application requirements this may or may not be possible. You will need to open a service request for more information.
National Instruments
FlexRIO Product Support Engineer

Sharing an external sample clock between PCI-6722 and PCI-6602

I need PCI-6602 work with PCI-6722。6602 shares 6722’s ao/SampleClock as external clock and triggered by 6722’s ao/StartTrigger。The master device is 6722, which refered as Dev1, and the slave device is 6602, which refered as Dev2. A RTSI line is used to connect the two devices correctly.
I use C API to finish my program and my code is as follows:
//config 6722 analog out task
1、DAQmxCreateTask("NI6672", &hAOTask);
2、DAQmxCreateAOVoltageChan(hAOTask, "Dev1/ao0", "", -10.0, 10.0, DAQmx_Val_Volts, "" );
3、DAQmxCfgSampClkTiming(hAOTask, "", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
4、DAQmxWriteAnalogF64(hAOTask, 1000, 0, 10.0, DAQmx_Val_GroupByChannel, data, NULL, NULL);
//config 6602 counter task
5、DAQmxCreateTask("NI6602", &hCounterTask);
6、DAQmxCreateCICountEdgesChan(hCounterTask, "Dev2/ctr0", "", DAQmx_Val_Rising, 0, DAQmx_Val_CountUp);
//use /Dev1/ao/SampleClock for external clock
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev1/ao/SampleClock", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
//use /Dev1/ao/StartTrigger
8、DAQmxSetTrigAttribute (hCounterTask, DAQmx_ArmStartTrig_Type, DAQmx_Val_DigEdge);
9、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Src, "/Dev1/ao/StartTrigger");
10、DAQmxSetTrigAttribute (hCounterTask, DAQmx_DigEdge_ArmStartTrig_Edge, DAQmx_Val_Rising);
//start counter task first
11、DAQmxStartTask(hCounterTask);
//start 6722 task
12、DAQmxStartTask(hAOTask);
I run it on the MAX virtual Device, and the Step 11always returned -89120。
I try to slove this problem, so I change the Step 7, use /Dev2/PFI9 to instead of /Dev1/ao/SampleClock.
7、DAQmxCfgSampClkTiming(hCounterTask, "/Dev2/PFI9", 1000.0, DAQmx_Val_Rising, DAQmx_Val_ContSamps, 1000);
The code runs well, but I don’t know which terminal is connected by /Dev2/PFI9. Does it connect to /Dev1/ao/SampleClock？
I use another API DAQmxConnectTerms to ensure that, I add a Step before Step 11.
DAQmxConnectTerms( "/Dev1/ao/SampleClock", "/Dev2/PFI9", DAQmx_Val_DoNotInvertPolarity );
The program also run well. But I am still not sure that 6602 is sharing /Dev1/ao/SampleClock。If not, which terminal of Dev1 is connected by /Dev2/PFI9?
Is my code right? If not, hwo to fix my code or supply some example for me? Thanks.

Hello Shokey,
From looking over your post, it looks like you want to program in C, using simulated instruments, a master/slave design with a PCI-6602 and PCI-6722. The PCI-6722 is the master device and the PCI-6602 is the slave device. In order to implement this with the real cards, you would need a RTSI cable between the 2 cards in order to pass the triggers and the sample clock. Unfortunately with simulated devices you can't implement this so parts of your code won't be able to work exactly like if you had the instrument.
If you did have the instrument, you can implement this by performing the following steps:
Master Device:
1.) Export the ao/SampleClock and ao/StartTrigger to a RTSI Line. (See DAQmx C Reference help for DAQmxExportSignal to export these)
Slave Device:
1.) Set the Sample clock and the trigger to the RTSI.
There is another forum that I think will help you out to implement this correctly. In this forum, the customer was trying to export a trigger through a RTSI and the problem he was experiencing was a broken RTSI cable. His code, he states, works. I hope this helps you with this and if you have any more questions, feel free to post.
Jim St
National Instruments
RF Product Support Engineer

9188 sample clock for Example VI

Hi,
I'm trying to run the Example VI: "Gen Event for Ext Signal" on Labview 10 with the NI cDAQ 9188. I'm getting an error (see below). I tried fixing this error by changing the code from "Hardware Timed Signal Point" to "Continuous" but then it seems my sample clock doesnt work. Any ideas what's going on?
>>>>>>>>
Error -200077 occurred at Property Node DAQmx Timing (arg 3) in DAQmx Timing (Sample Clock).vi:2->Gen Event for Ext Signal.vi
Possible reason(s):
Requested value is not a supported value for this property. The property value may be invalid because it conflicts with another property.
Property: SampQuant.SampMode
Requested Value: Hardware Timed Single Point
You Can Select: Finite Samples, Continuous Samples
Task Name: _unnamedTask<296B>
>>>>>>>>>>

Hi there roto,
Does the following link help?
NI-DAQmx Hardware-Timed Single Point Support for Oversample Clock Timed Devices: http://zone.ni.com/devzone/cda/pub/p/id/1325
Best,
Ryan C.
Applications Engineer
National Instruments

Daqmx Sample clock

Hello,
I am using Daqmx Sample clock function and I am a little confused about the input " rate" of this function.
In Labview Help, this inut is defined as below:
"rate" specifies the sampling rate in samples per channel per second.
Now I set this " rate" to be 8000 and I have 8 channels, Does this mean that the sampling rate of the whole device is 64000? The samples per channel is 1000, what is the buffer size allocated by labview? Is it 8000?
Thanks in advance, I am looking forward to the replies.

Below is another knowledge base article.
http://digital.ni.com/public.nsf/3efedde4322fef19862567740067f3cc/dbe7ac32661bcf9b86256ac000682154?OpenDocument
You said that you have eight channels. Are these channels setup in MAX and if so are they global channels or just one Task? Or are you creating a Task in LabVIEW?
If you are reading these channels as a single Task, then each channel is being sampled at "sample rate". Then the buffer size is dependent on "sample mode". If it is continuous then use the chart, but if "Sample Mode" is finite then, NI-DAQmx allocates a buffer equal in size to the value of samples per channel.
When doing finite, "sample rate" is the rate at which the channel will be sampled and "samples per channel" is the number of samples to return. So if sample rate = 1000 and number of samples to return = 100, then 100mSeconds of data will be returned ("number of samples to return/"sample rate"). In other words the channel will be sampled at 1000 until a total of 100 samples has been received.
Chad

Sample clock source through RTSI

Hello,
I have a short question on a sample clock source through RTSI.
In my setup, two PCI cards (PCI-6602 (dev2) and PCI-6110 (dev1)) are connected through a RTSI cable.
I'd like to generate a sample clock source on 6110 and use it on 6602 to count external input pulses.
In MAX test panel, I checked a counter was reading the external signals.
However, the attached vi do not work and count at all, then give an error of 200284.
Could you tell me what is wrong?
I guess something is not right on routing the clock signal. Do I need to use DAXmx connect terminals vi instead of external signal?
How can I check the two devices are connected properly through a RTSI cable?
I registered the cable and connected the devices on MAX without any issues. Is that enough?
Thank you for your kind suggesion and comments.
Solved!
Go to Solution.
Attachments:
block.jpg ‏108 KB
front.jpg ‏86 KB

Hi Sugar7,
There are some more simple ways of using the hardware clock on the 6110 as the timebase of the 6602. I have attached a code that shows how the timing property node can be used to set the timebase of the 6602 task. The attached screen shot also shows this property node. Using this property node, you will no longer need the counter output task from the 6110, so the only task line will be the counter acquire task.
The other change that you might consider is changing the sample mode of the sample clock to finite samples as you seem to be acquiring a finite number of samples before the task ends. If you would like the code to continue acquiring data points, then you may want to utilize a while loop around the read operation.
Ben R.
Modular Instruments Product Marketing Engineer
National Instruments
Attachments:
RTSI Clock Reference.png ‏124 KB
Timebase node.png ‏3 KB

Device supports sample clock input

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