FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17

Question

I have got "FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.17" twice now during FPGA compiles. Oddly enough, the first time it happened, a new compile attempt was all it took to fix it. I am recompiling now after it happened after a compile of a new design. Any idea how to fix it?
I'll attach the compiler output.
Edit: The smiley above is a colon then a capital P.
Message Edited by pd2 on 06-23-2008 02:08 PM
Attachments:
compile failure.txt ‏511 KB

Answer 1

Hi PD2
First, in terms of adding and configuring a clock to the project, the method you state should be OK.
Concerning the errors you are getting, I have not run into them before.  My expertise with this module is coming more from the RF side of the module that the FPGA side.  I looked at your VI though, and I am not comfortable with the way you have configured your filters, mainly the use of arrays.  Also the multiple arrays in inside a cluster.  I have not been that successful writing code like this before so I am not sure how feasible this is when compiling.  One suggestion I have to see if this is an issue or not would be to reduce the size of the arrays down to three elements each. I know this will not be a feasible filer for you, but if the code starts compiling without any errors, it may be a sign that the code might be a little complex for the compiler.  Also, the fact that you seem to be running a 75 tap filter, and twice, might be too much for the compiler for the IF-RIO’s FPGA.
I’ve attached a filter that we have implemented in two projects here.  It is very pipelined as well as reusing multipliers.  The VI must run in a SCTL loop that is running at least as twice as fast as the ADC IQ rate.  This is due to a MUX internal that switches whether an I or Q sample is directed to the multipliers.  In this way, the multipliers on the FPGA do double duty, and we minimize the number of multipliers used.
The other important feature to point out about the code is that the coefficients of the filter are “clocked” into the FPGA at the beginning through one front panel control (vs. an array) before processing starts.  Also, the coefficients in the array. The array manipulation itself, are not processed though every clock of the SCTL loop. 
The compilers should spread out every element of the arrays and arrays in the clusters to individual data lines so that the data can process on every cycle of the clock.  But I have had issues in the past where I have used clusters and I have been unable to compile the code.  I usually minimize the use of clusters and arrays that I now use, especially when putting arrays in clusters.
I hope this helps.
Jerry
Message Edited by Jerry_L on 07-07-2008 11:30 AM
Attachments:
FilterEx.zip ‏945 KB