FATAL_ERROR:Xst:....

Greetings to all,
Two questions:
1) We were trying to compile an FIR project on the FPGA and we faced several problems. After 15 hours of compilation, the following error was popped out:
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.13.276.1 -
This application has discovered an exceptional condition from which it cannot recover. Process will terminate.
ERROR:Xflow - Program xst returned error code 1. Aborting flow execution...
We also noticed the following during compilation: "INFO:Xst:738 - HDL ADVISOR - 640 flip-flops were inferred for signal <out_l>. You may be trying to describe a RAM in a way that is incompatible with block and distributed RAM resources available on Xilinx devices, or with a specific template that is not supported. Please review the Xilinx resources documentation and the XST user manual for coding guidelines. Taking advantage of RAM resources will lead to improved device usage and reduced synthesis time"
and we don't know the cause of such problem? Do you have any hints?
2) When creating a real time application between the host VI and the FPGA VI, we put a timed loop on the FPGA VI, and then read the values using the read/write
control function in a while loop on the HOST VI. How can we know how often the host read/write control function reads a value from the FPGA VI.
Does the read/write control function reads a value from the FPGA on every iteration of the FPGA loop? If No, what controls the iteration duration on the HOST VI?
In other words, How does the while loop in the HOST VI synchronize with the FPGA timed loop?
P.S. Putting a timed loop on the HOST VI is not an option becuase the used dt on the FPGA VI is too small (corresponding to a zero on the HOST)

Hello,
1.
We are also seeing the following error message:
WARNING:Xst:524 - All outputs of the instance <TimeoutManagerx> of the block <TimeoutManager> are unconnected in block <FifoPopControl>. This instance will be removed from the design along with all underlying logic
FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.13.276.1 -
This application has discovered an exceptional condition from which it cannot recover.
ERROR:Xflow - Program xst returned error code 1. Aborting flow execution...
"the Xilinx compiler can take very long
times to compile FPGA >code that contain arrays, and this has led to the
compiler ending with an error."
In our case the compilation ran for 1.5 hours on a Pentium III with 512MB RAM; could this still be the cause ?
2.
We are using two 16-bit arrays (from a front-panel connector) and four 32-bit arrays (from a global variable). The arrays size is 64 elements.
We do not have 'create arrays' and 'array local variables'. However, we do have a for loop with replace array subset and I would like to know what kind of overhead that may cause ?
In previous iterations, we had longer compilation times when we were using larger arrays and were passing them between sub-VIs and the process ran out of memory.
3.
We will be modifying the code to indexed memory operations, but would like to understand better the workings of arrays. The overheads to be expected when using arrays seem to be very high from our experience. Any suggestions on the maximum size after which problems can be expected ? Or best-use practices for array operations would be welcome.
Thanks in advance.
Regards,
Manik

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FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.17

I have got "FATAL_ERROR:Xstortability/export/Port_Main.h:127:1.17" twice now during FPGA compiles. Oddly enough, the first time it happened, a new compile attempt was all it took to fix it. I am recompiling now after it happened after a compile of a new design. Any idea how to fix it?
I'll attach the compiler output.
Edit: The smiley above is a colon then a capital P.
Message Edited by pd2 on 06-23-2008 02:08 PM
Attachments:
compile failure.txt ‏511 KB

Hi PD2
First, in terms of adding and configuring a clock to the project, the method you state should be OK.
Concerning the errors you are getting, I have not run into them before. My expertise with this module is coming more from the RF side of the module that the FPGA side. I looked at your VI though, and I am not comfortable with the way you have configured your filters, mainly the use of arrays. Also the multiple arrays in inside a cluster. I have not been that successful writing code like this before so I am not sure how feasible this is when compiling. One suggestion I have to see if this is an issue or not would be to reduce the size of the arrays down to three elements each. I know this will not be a feasible filer for you, but if the code starts compiling without any errors, it may be a sign that the code might be a little complex for the compiler. Also, the fact that you seem to be running a 75 tap filter, and twice, might be too much for the compiler for the IF-RIO’s FPGA.
I’ve attached a filter that we have implemented in two projects here. It is very pipelined as well as reusing multipliers. The VI must run in a SCTL loop that is running at least as twice as fast as the ADC IQ rate. This is due to a MUX internal that switches whether an I or Q sample is directed to the multipliers. In this way, the multipliers on the FPGA do double duty, and we minimize the number of multipliers used.
The other important feature to point out about the code is that the coefficients of the filter are “clocked” into the FPGA at the beginning through one front panel control (vs. an array) before processing starts. Also, the coefficients in the array. The array manipulation itself, are not processed though every clock of the SCTL loop.
The compilers should spread out every element of the arrays and arrays in the clusters to individual data lines so that the data can process on every cycle of the clock. But I have had issues in the past where I have used clusters and I have been unable to compile the code. I usually minimize the use of clusters and arrays that I now use, especially when putting arrays in clusters.
I hope this helps.
Jerry
Message Edited by Jerry_L on 07-07-2008 11:30 AM
Attachments:
FilterEx.zip ‏945 KB

[SOLVED] moc: "FATAL_ERROR: No valid sound driver! Server exited!"

mocp
Running the server...
Trying JACK...
Trying ALSA...
ALSA lib pcm_hw.c:1741:(_snd_pcm_hw_open) Unknown field mmap_emulation
ALSA lib pcm_dmix.c:1022:(snd_pcm_dmix_open) unable to open slave
Trying OSS...
FATAL_ERROR: No valid sound driver!
FATAL_ERROR: Server exited!
so some time ago i messed up the sound badly and now i'm clueless on what to do. i have alsa, oss and pulseaudio (re-re-re-re-re)installed (i know i shouldn't). i'm a total noob when it comes to the audio department so i can't really add way too much to it.
audacious drops the following when i try to play something:
ALSA error: snd_pcm_open failed: Invalid argument.
there is audio, however (some games/web) if i pulseaudio --start.
pls ask for outputs to give you the necessary info
Last edited by wootsgoinon (2014-02-11 23:37:15)

did you have working audio before you did something that messed it up?
alsa is pretty much all you need for working audio. You could run pulseaudio on top of it if you want, but usually it doesn't benefit you in any way unless you have some specific issues with alsa, like audio only playing from one application at the time.
You can safely remove everything OSS related, unless you actually want to configure your system to use OSS for some reason.
If you want to revert to default your alsa configuration you could just remove your ~/.asoundrc and /etc/asound.conf if you have modified those files. If you want to use pulseaudio, reinstall pulseaudio-alsa to revert /etc/asound.conf configuration so that your alsa-only applications work with pulse.

WARNING:UtilitiesC - Message file "Xst.msg" wasn't found.ERROR:PersonalityModule

when i am trying to check syntax of my code in HDL Interface Node following errors had been occured
Release - xst J.33
Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved.
WARNING:UtilitiesC - Message file "Xst.msg" wasn't found.
--> WARNING:UtilitiesC - Message file "PersonalityModule.msg" wasn't found.
ERRORersonalityModule - Unable to open definition file for Personality Module "virtex". Please make sure that it has been correctly installed.

Hello Jonah,
i was trying to implemet and addition of two numbers in Verilog code . I used NGC netlist file in the external files of the HDL Interface node. While checking for the syntax error, i getting the error.
i am attaching the program and also the screen shot of the error.
thanks,
sriveni.
Attachments:
Error while Checking Syntax.JPG ‏49 KB
Program.zip ‏175 KB

Exception Condition "Fatal_Error" Raised in SMQ2

Hi,
I am doing File to Proxy(ECC) Asynchronous scenario. in this getting the error in Target side(ECC) in SMQ2 message is showing error , when I double click on this error getting the error message like Exception Condition "Fatal_Error" Raised.
Because of this interface error Remaining interfaces also getting failure.
these interfaces was working fine.
I searched in SDN, but i didn't get proper solution for related to this issue.Pl suggest us to resolve this issue.
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Hi Pasi,
This looks like a data issue which has resulted in an exception in Proxy code. If this is not a production system I will suggest you to delete the error entry from queue and test with an older successful data and see whether it gets successfully executed or not.
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Compilation error - FPGA NI PXI-7951R board - ERROR: Xst: 2472 - Top module Puma15Top was not found.

I'm trying to compile a "user CLIP socket" for the NI PXI board - 7951R which has a Virtex-5 LX30 FPGA from Xilinx, but I got the bellow message from NI Compiler, this message is in error report Xilinx.log.
It says that module Puma15Top was not found.
But this module is a NI property and is automatically compiled by NI Compiler.
The compiler automatically generates these files (Puma15Top...) that are passed to the compiler of Xilinx. The Puma15Top files are in the path, i.e: C: \ NIFPGA \ compilation \ Told_F_I_CC5DC260 \ source_files.
This folder name is automatically generated by labview (Told_F_I_CC5DC260) for each different project or compilation.
So I have no way to configure in CLIP files where it'll be Puma15Top, once the path is automatically generated during compilation by Labview.
Does anyone have any idea how to solve this problem? Or have you experienced some like this?
Following error log:
### XstSynthesis ###
Puma15Top
Reading design: Puma15Top.prj
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_Conf.vhd" in Library work.
Entity <CLUC001_Conf> compiled.
Entity <CLUC001_Conf> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/NIFPGA/jobs/Cm9xA8x_LaF6U1d/CLUC001_CLIP.vhd" in Library work.
Entity <CLUC001_CLIP> compiled.
Entity <CLUC001_CLIP> (Architecture <rtl>) compiled.
Entity <CLUC001_CLIP> (Architecture <behavioral>) compiled.
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Thanks in advanced!

Hi Guilherme,
Thanks your suggestion, I upgraded NI-RIO to 13.1.1 version but the problem persists, as shown below:
Project: T_old.lvproj
Target: F (RIO0, PXI-7951R)
Build Specification: I_2
Top level VI: I.vi
Compiling on local compile server
Compilation Tool: Xilinx 11.5
Start Time: 2/9/2014 18:03:51
Run when loaded to Fpga: FALSE
JobId: z8Cq8B4
Working Directory: C:\NIFPGA\compilation\Told_F_I2_F3177096
Compilation failed due to a Xilinx error.
Details:
ERROR:Xst:2472 - Top module <Puma15Top> was not found.
ERROR:Xst:2469 - Please specify the correct library via the -work_lib switch.
-->
Total memory usage is 149596 kilobytes
Number of errors   :    2 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)
Process "Synthesis" failed
Start Time: 18:03:51
End Time: 18:05:19
Total Time: 00:01:27,414
Best,
JEMP

WARNING:Xst:1290 - Hierarchical block is unconnected in block core . It will be removed from the design.

Hi ,
I have been using ISE for some time. However suddenly without any changes to the design, when I tried synthesis today i got many errors liek the following :
WARNING:Xst:1290 - Hierarchical block <credit_sync_wrapper_I> is unconnected in block <core>.
It will be removed from the design.
Is there any way to prevent ISE from freely removing blocks even though they are clearly connected by signals which can change in any clock cycle. Perhaps a global setting for preventing such optimizations ?

anandy wrote:
Hi ,
I have been using ISE for some time. However suddenly without any changes to the design, when I tried synthesis today i got many errors liek the following :
WARNING:Xst:1290 - Hierarchical block <credit_sync_wrapper_I> is unconnected in block <core>.
It will be removed from the design.
Is there any way to prevent ISE from freely removing blocks even though they are clearly connected by signals which can change in any clock cycle. Perhaps a global setting for preventing such optimizations ?
In general, XST will only remove logic that does not affect any outputs of the overall design.
It is unreasonable that XST would "suddenly without any changes to the design" rip out logic
that was included in a previous build. You are re-running XST, so something must have
"changed in the design." You could instruct XST to leave it all in, but you would then end up with
a design that has more logic, but no more functionality that the one that left it all out.
The most common reasons for large sections of a design to suddenly get ripped out are
missing clocks or constantly asserted resets. Either of these will cause all the downstream
logic to get replaced with constants, and hence ripped out of the design.
-- Gabor

ERROR:Xst:827 - Signal ig_s cannot be synthesized, bad synchronous description.

i am getting the error ERROR:Xst:827 - Signal ig_s cannot be synthesized, bad synchronous description. The description style you are using to describe a synchronous element (register, memory, etc.) is not supported in the current software release.
my code is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mod16 is
port(
clk : in std_logic; -- global clock
rst : in std_logic; -- asynchronous active high reset
din : in std_logic_vector(3 downto 0); -- data in
sum : out unsigned(31 downto 0); --final output
carry_out : out std_logic
end mod16;
architecture Structural of mod16 is
component mapper is
port
clk, rst : in std_logic; -- global clock
m_in : in std_logic_vector(3 downto 0); -- data in
rl,ig : out std_logic_vector(15 downto 0) -- real and imaginary out
end component;
component upsampller is
port
s_in : in std_logic_vector(15 downto 0);
s_out : out std_logic_vector(15 downto 0);
clk : in std_logic;
rst : in std_logic
end component;
component fir_16tap is
port
clk : in std_logic; --clock signal
f_in : in std_logic_vector(15 downto 0); --input signal
f_out : out signed(23 downto 0) --filter output
end component;
component coswave is
port (clk :in std_logic;
cos_out : out integer range -128 to 127
end component;
component sinewave is
port (clk : in std_logic;
sine_out : out integer range -128 to 127
end component;
component multiplier is
port
mul_in1 : in signed(23 downto 0);
mul_in2: in integer range -128 to +127;
mul_out: out std_logic_vector(39 downto 0)
end component;
component adder is
port
in1, in2 : in std_logic_vector(39 downto 0);
sum : out unsigned(39 downto 0);
carry_out : out std_logic
end component;
signal rl_s1,ig_s1, up_s1, up_s2 : std_logic_vector(15 downto 0);
--signal up_s1, up_s2 : signed(15 downto 0);
signal f_out_s1, f_out_s2 : signed(23 downto 0);
signal cos_out_s, sine_out_s : integer range -128 to +127;
signal mul_out_s1, mul_out_s2: std_logic_vector(39 downto 0);
signal sum_out_s : unsigned (39 downto 0);
signal carry_out_s : std_logic;
begin
u1:mapper port map(clk => clk, rst => rst, m_in => din, rl => rl_s1, ig => ig_s1);
u2:upsampller port map(s_in => rl_s1, clk => clk, rst => rst, s_out => up_s1);
u3:upsampller port map(s_in => ig_s1, clk => clk, rst => rst, s_out => up_s2);
u4:fir_16tap port map(clk => clk, f_in => up_s1, f_out => f_out_s1);
u5:fir_16tap port map(clk => clk, f_in => up_s2, f_out => f_out_s2);
u6:coswave port map(clk => clk, cos_out => cos_out_s);
u7:sinewave port map(clk => clk, sine_out => sine_out_s);
u8:multiplier port map(mul_in1 => f_out_s1, mul_in2 => cos_out_s, mul_out => mul_out_s1);
u9:multiplier port map(mul_in1 => f_out_s2, mul_in2 => sine_out_s, mul_out => mul_out_s2);
u10:adder port map(in1 => mul_out_s1, in2 => mul_out_s2, sum => sum_out_s, carry_out => carry_out_s);
end Structural;
and code of mapper is
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- entity declaration
entity mapper is
Port ( clk, rst : in std_logic; -- global clock
--reset : in std_logic; -- asynchronous active high reset
--valid_in : in std_logic; -- when high din is valid
m_in : in std_logic_vector(3 downto 0); -- data in
rl,ig : out std_logic_vector( 15 downto 0) -- real out
--ig : out std_logic_vector(15 downto 0)-- imag out
--valid_out : out std_logic -- when high real and imag is valid
end mapper;
-- architecture declaration
architecture Behavioral of mapper is
--signal count : std_logic;
signal rl_s : std_logic_vector(15 downto 0);
signal ig_s : std_logic_vector(15 downto 0);
begin
-- process to map 16 point constellation
process(clk, rst)
begin
--if(rst = '1') then
--rl_s <= (others => '0');
--ig_s <= (others => '0');
--count <= '0';
--valid_out <= '0';
if(clk'event and clk = '1') then
--if(valid_in = '1') then
--count <= '0';
case m_in is
when"0000" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"0001" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"0010" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"0011" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"C349"; --x"FF0D";
--valid_out <= '1';
when"0100" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"0101" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"0110" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"0111" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"C349"; --x"FFC3";
--valid_out <= '1';
when"1000" =>
rl_s <= x"EBC3";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"1001" =>
rl_s <= x"EBC3"; --x"FFAE";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"1010" =>
rl_s <= x"EBC3"; --x"FFAE";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"1011" =>
rl_s <= x"EBC3"; --x"FFAE";
ig_s <= x"C349"; --x"FF0E";
--valid_out <= '1';
when"1100" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"1101" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"1110" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"1111" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"C349"; --x"FF0E";
--valid_out <= '1';
when others => null;
end case;
else
rl_s <= (others => '0');
ig_s <= (others => '0');
--valid_out <= valid_in;
end if;
--end if;
end process;
rl <= rl_s;
ig <= ig_s;
end Behavioral;
please reply
thanx

still same error
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- entity declaration
entity mapper is
Port ( clk, rst : in std_logic; -- global clock
--reset : in std_logic; -- asynchronous active high reset
--valid_in : in std_logic; -- when high din is valid
m_in : in std_logic_vector(3 downto 0); -- data in
rl,ig : out std_logic_vector( 15 downto 0) -- real out
--ig : out std_logic_vector(15 downto 0)-- imag out
--valid_out : out std_logic -- when high real and imag is valid
end mapper;
-- architecture declaration
architecture Behavioral of mapper is
--signal count : std_logic;
signal rl_s : std_logic_vector(15 downto 0);
signal ig_s : std_logic_vector(15 downto 0);
begin
-- process to map 16 point constellation
process(clk, rst)
begin
if(rst = '1') then
rl_s <= (others => '0');
ig_s <= (others => '0');
--count <= '0';
--valid_out <= '0';
elsif(clk'event and clk = '1') then
--if(valid_in = '1') then
--count <= '0';
case m_in is
when"0000" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"0001" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"0010" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"0011" =>
rl_s <= x"143d"; --x"0051";
ig_s <= x"C349"; --x"FF0D";
--valid_out <= '1';
when"0100" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"0101" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"0110" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"0111" =>
rl_s <= x"3CB7"; --x"00F2";
ig_s <= x"C349"; --x"FFC3";
--valid_out <= '1';
when"1000" =>
rl_s <= x"EBC3";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"1001" =>
rl_s <= x"EBC3"; --x"FFAE";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"1010" =>
rl_s <= x"EBC3"; --x"FFAE";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"1011" =>
rl_s <= x"EBC3"; --x"FFAE";
ig_s <= x"C349"; --x"FF0E";
--valid_out <= '1';
when"1100" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"143d"; --x"0051";
--valid_out <= '1';
when"1101" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"3CB7"; --x"00F2";
--valid_out <= '1';
when"1110" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"EBC3"; --x"FFAE";
--valid_out <= '1';
when"1111" =>
rl_s <= x"C349"; --x"FF0E";
ig_s <= x"C349"; --x"FF0E";
--valid_out <= '1';
when others => null;
end case;
--else
--rl_s <= (others => '0');
--ig_s <= (others => '0');
--valid_out <= valid_in;
end if;
--end if;
end process;
rl <= rl_s;
ig <= ig_s;
end Behavioral;

Error compiling FPGA VI: ERROR:Xflow - Program xst returned error code 6.

When I use the Linear Interpolation function in my FPGA VI i get the compilation error:
ERROR:Xflow - Program xst returned error code 6. Aborting flow execution...
the Compile Server also gives the more detailed information:
ERROR:Xst:1749 - "C:/NIFPGA85/srvrTmp/LOCALH~1/TRAPCO~2/NiLvFxpFloor.vhd" line 68: error: The output for the floor function should not have any fractional bits.
I'll be happy for any suggestions how to solve this.

Hello!
Could you compile a program with only the Linear Interpolation.vi and only some constants and indicator as input and output?
I tried on my PC and compile a simple VI containing only the Linear Interpolation.vi
Which Version of NI-RIO do you use?
Do you also placed the FPGA VI in library? If yes put out all FPGA VIs from the library and check that they aren't reentrant.
This could cause problems to the compiling of FPGA VI.
Try to create a new project with only a VI with the linear interpolation and check if it is compiled.
Best regards
Ken

Project with PmodCLP module cannot synthesize --INTERNAL_ERROR:Xst:cmain.c:3423:1.29

Hey guys, I'm working on a project with a PmodCLP module. The PmodCLP module transfers data to a 16X2 LCD with a parallel interface. And I modified a demo code （ref:demo code)to adjust to my project, which resulted in an INTERNAL_ERROR:Xst:cmain.c:3423:1.29.(The demo code works perfect)
By searching for solutions, I have narrowed down that the problem is caused by (see the files attenched for complete code )
signal LCD_CMDS : LCD_CMDS_T := ( -- I changed constant to signal
0 => "00"&X"3C", --Function Set
1 => "00"&X"0C", --Display ON, Cursor OFF, Blink OFF
2 => "00"&X"01", --Clear Display
3 => "00"&X"02", --return home
4 => "10"&X"02", - -----the original demo code writes constant chars to LCD
--##################################### -- I want to transfer changable content
11 => "10" & sl2asc(mid_reg7(3 downto 0)), --code std_logic_vector to asc code
12 => "10"&X"20" --blank
); --Shift left
In the demo code, LCD_CMDS is constant, and I changed it to signal, then the error occured. Any ideas to fix the problem?

An INTERNAL_ERROR indicates that the tool was not able to handle the HDL code in this scenario.
Can you share the synthesis report , so that i can verify and suggest details?
Regards,
Achutha

FATAL_ERROR in CRM outbound queue

Hi,
In CRM Outbound queue SMQ1 (SALES ORDER) we are getting some dumps as follows.
Exception condition "FATAL_ERROR" raised.
But in ST22, I cannot see any dumps caused by this. Please help.
Thanks & Regards
Sunil

Hello Sunil,
look up the function call used in doc flow by clicking on the bdoc.
Set a breakpoint there.
Lookup error nummer and error class (you can search all error text in table t100)
Set a conditional breakpoint on sy-msgno with condition sy-msgno = <yournumber>
Let the code itself tell you why you get a fatal error.
You might want to check the general connectivity betweeen crm and erp as well.
Are there any green bdocs exchanged betweeen the Systems?
Greetings Lutz

Xst:1290 and 2677

Hi.
I am trying to desing a UART module. I have a DCM clock module and a baud rate generator. My BaudGenerator produces an enable signal (en) which I use in the processes (now it's just a test) to do send and receive. My enable signal is checked in the process, but I get these warnings and my BaudGenerator won't show up in RTL:
WARNING:Xst:1290 - Hierarchical block <BaudGenerator1> is unconnected in block <TopModule>.
It will be removed from the design.
WARNING:Xst:2677 - Node <BaudGenerator1/en> of sequential type is unconnected in block <TopModule>.
I will be so thankful if you can help me solve this problem.
The code for my top module is:
ENTITY TopModule IS
PORT (clk_in : IN STD_LOGIC;
reset : IN STD_LOGIC;
uart_tx : OUT STD_LOGIC;
uart_rx : IN STD_LOGIC);
END TopModule;
ARCHITECTURE Behavioral OF TopModule IS
COMPONENT ClockDivider
PORT(
CLKIN_IN : IN STD_LOGIC;
RST_IN : IN STD_LOGIC;
CLKFX_OUT : OUT STD_LOGIC;
CLKIN_IBUFG_OUT : OUT STD_LOGIC
END COMPONENT;
COMPONENT BaudGenerator
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
en : OUT STD_LOGIC);
END COMPONENT;
SIGNAL clk : STD_LOGIC;
SIGNAL en : STD_LOGIC;
SIGNAL rx_buffer : STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
SIGNAL tx_buffer : STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0');
BEGIN
ClockDivider1: ClockDivider PORT MAP(
CLKIN_IN => clk_in,
RST_IN => reset,
CLKFX_OUT => clk,
CLKIN_IBUFG_OUT => open
BaudGenerator1: BaudGenerator PORT MAP(
clk => clk,
reset => reset,
en => en
RECEIVE: PROCESS (clk)
BEGIN
IF RISING_EDGE (clk) THEN
IF (en = '1') THEN
rx_buffer <= "11000101";
END IF;
END IF;
END PROCESS;
And my BaudGenerator is:
ENTITY BaudGenerator IS
PORT (clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
en : OUT STD_LOGIC);
END BaudGenerator;
ARCHITECTURE Behavioral OF BaudGenerator IS
CONSTANT N : STD_LOGIC_VECTOR (3 DOWNTO 0) := "1111";
SIGNAL count : STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
BEGIN
PROCESS (clk)
BEGIN
IF RISING_EDGE (clk) THEN
IF (reset = '1') THEN
count <= (OTHERS => '0');
en <= '0';
ELSE
IF (count = N) THEN
count <= (OTHERS => '0');
en <= '1';
ELSE
en <= '0';
count <= STD_LOGIC_VECTOR (UNSIGNED (count) + 1);
END IF;
END IF;
END IF;
END PROCESS;
END Behavioral;

Well :-P
Since I was not using the buffer anywhere else, it can be said that the BaudGenerator module was not doing anything useful, so the tool was trimming the module.

XST producing seemingly random results

Hi,
I have a circuit which I am synthesizing in XST and eventually building into a bit file. The problem is that some times the bitfile doesn't work and simply regenerating the netlist with a change in some parameter (say Safe Implementation) and no changes in verilog generates a bitfile that works. Thus every change to the verilog I make is resulting in this frustrating cycle ot synthesize-test-synthesize again-test again.
I brought out some of the internal signals of the design out and the times when the design fails, the condition that it fails on is impossible with the correct interpretation of my verilog (1 signal is an input two 2 modules. One of the modules waits infinitely for that signal to become valid while the other proceeds).
Also, post synthesis simulation works in both cases. I am pretty much at my wits end here.
Any help would be greatly appreciated.
EDITL I'm using 12.4
Thanks!

Bad results from synthesis are rare in my experience. Unless you are comparing specific netlist-level logic which is seen to be incorrect in FPGA Editor (I've even seen a false positive here from the Technology Viewer schematic view), it is much more likely that another problem exists, which might include:
-unconstrained timing paths
-incorrect timing constraint (e.g. period of 10ns instead of 8ns)
-part below correct voltage, too much voltage ripple, too high of Tj for device), etc.
-incorrect I/O standard, wrong Vcco, etc.
-unconstrained I/O placement (<100% LOCed IOBs in map report) and actual placement varies between runs. Sometimes where you want it to really be. Sometimes not
-flip flops not being packed into IOB and FPGA-level set-up/hold time and/or clock-to-out varies between runs based on actual placement
-difference in BUFG/DCM placement impacting external effective FPGA timing
-running component outside of its spec (e.g. not following DCM high/low input/output rates for respective DLL & DFS range)
-targetting wrong speed grade part (e.g. -2 instead of -1)
-inproperly synchonized inputs to state machine
-clock issue, including improperly handling clock domain interfacing
-reset issue (e.g. asynchronous reset causing issue with one-hot state machine initialization)
-uncovered logic condition that fails to show up in simulation
-using a different clock and/or frequency that you think you are
-other board level issue other difficult to troubleshoot issue: simultaneous switching output, crosstalk, too much ripple on adjacent memory interface termination voltage, etc.
Yes, I've seen all of these...
Other useful info:
http://www.xilinx.com/products/quality/fpga_best_practices.htm (FPGA Design Best Practices)
bt

Conversion of XST file to XML file and vice a versa

Hello All,
I am working on one of the SAP-DMS issue.
Here my requirement is converting the XML file to XST file and vice a versa.
I tried to find out the possible solutioin but not succeed yet...
Please can anyone help with the solution?
Regards,
Reshma

Why don't try with Message Tran Bean
Check this below details out:
Processing Sequence:
1 localejbs/Seeburger/solution/sftp Local Enterprise Bean solutionid
2 localejbs/AF_Modules/MessageTransformBean Local Enterprise Bean mtb
3 localejbs/CallSapAdapter Local Enterprise Bean exit
Module Configuration:
mtb Transform.Class com.sap.aii.messaging.adapter.Conversion
mtb Transform.ContentType text/xml;charset=utf-8
mtb xml.conversionType SimplePlain2XML
mtb xml.documentName XXX_EXPENSES_mt
mtb xml.fieldContentFormatting trim
mtb xml.fieldNames FIELD1,FIELD2,FIELD3,FIELD4
mtb xml.fieldSeparator '0x09'
mtb xml.processFieldNames fromConfiguration
mtb xml.structureTitle RECORD
Regards
Pothana

XST Post-synthesis simulation differences between Virtex4 and Virtex6

Hi
I've been looking at a problem we've been having in one of our components where a register interface that we have implemented doesn't seem to be behaving correctly. We've used ISE 14.1 and 14.6, and simulated in ISim and ModelSim 6.6d, which both display the weird behavior. I've attached the project, source, simulation and post-synthesis code which display the issue.
We write a value (0x3FFF) to a register (in the case of the simulation 0xC) When that register is read back, we would expect 0x3FFF on reg_response_rdata. Indeed with pre-synthesis simulation, and post-synthesis on Virtex4, this is what we find. However on Virtex6 the response is 0x8000. Through trial and error we can fix this by changing line 98 of the source to the commented out line 99. Note that the implementation of pad_reg and pad_vector are identical, save for pad_vector taking the length as an argument.
To recreate run ab_dc.do in your favourite simulator. This simulates a register write to pre and post synthesis models. Notice the reads return different results depending on which hardware has been synthesised, and depending on whether pad_reg or pad_vector are used. Note also that the change to fix the behavior on line 98/99 isn't the same register that we try to write to/read from.
When it is broken (ie using pad_reg) we get the following warning: WARNING:Xst:2999 - Signal 'debug_counter', unconnected in block 'ab_dc_pre_comp', is tied to its initial value. I'm not sure what the initial value of debug counter can/should be. This warning doesn't appear when using pad_vector.
Files in zip:
./ab_dc.vhd                                                                                The source
./WarningOutput.txt                                                                   A comparision of the warnings from ISE14.1 when compiling for Virtex6. Broken = pad_reg, Fixed = pad_vector
./xilinxTest.ise                                                                           The ISE project file
./netgen/synthesis/v4_ab_dc_comp_synthesis.vhd                  ab_dc.vhd synthesised for Virtex4 using ISE14.1 using pad_reg
./netgen/synthesis/v6_ab_dc_comp_synthesis.vhd                  ab_dc.vhd synthesised for Virtex6 using ISE14.1 using pad_reg
./netgen/synthesis/v6_fix_ab_dc_comp_synthesis.vhd            ab_dc.vhd synthesised for Virtex6 using ISE14.1 using pad_vector
./sim/ab_dc.do                                                                           TCL to compile and run simulation
./sim/ab_dc_tb.vhd                                                                    Simulation to write to register 0xC and then read from it.
./sim/wave.do                                                                            Useful signals to recreate problem
This looks to me like a bug in XST. I'm happy to be proven wrong though!
Thanks

Looks like a parser issue to me, in case of V4 device XST uses an old parser and for V6 devices XST uses new parser. Check below AR:
http://www.xilinx.com/support/answers/32927.html
Thanks,
Anusheel
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.
Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
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FATAL_ERROR:Xst:....

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