Finite pulse train generation?

i am trying to generate a very specific pulse with my tio-6602 in labwindows. after a 20us delay, i want the board to generate 20 pulses, with a width of 1 us and an interval of 5us. ideally, this would be retriggerable at 100 Hz. any suggestions on what would be the best way to approach this problem?

Paco,
You can use a gated pulse train, which is similar to finite pulse train generation. With finite pulse train generation, you have one pulse for the gate of a counter set to generate a pulse train. The pulse train will only be output based on the gate, so if one pulse appears, you have a finite pulse train. Now, if you make the gate be a pulse train itself, then you can continuously output bursts of pulses. For instance, you can set it up such that the pulses are output when the gate is high. When the gate is low, the counter pulses would pause and when the gate resumes to the high states, your pulses would continue. I've attached a code excerpt for using NI-DAQ function calls to generate a finite pulse train that is in our database. I will see abo
ut getting it put onto the http://www.ni.com/support pages. You can also find more information about the function calls used by referencing the NI-DAQ Help file installed with the NI-DAQ driver software and with the NI-DAQ User Manual, which is available at the web pages.
Regards,
Geneva L.
Applications Engineering
National Instruments
http://www.ni.com/ask
Attachments:
finitepulsetrain.txt ‏2 KB

Similar Messages

Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
My question is, Is there any way to do the finite pulse train generation, unreserve the counters, wait for a finite count to finish and so on?
Thanks.

Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
However, the finite pulse train generation and the continuous pulse train generation seem similar. The key difference is the generation mode from continuous to finite and the use fo a DAQmx Wait Until Done vi instead of a loop to monitor user input. From a point of view of the hardware there is a difference between the two. Continuous pulse train generation requires only 1 COUNTER.
Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

Finite pulse train generation... how to count number of pulses?

hi guys,
this has probably been solved a hundred times but i just couldnt find it!!
i have a pulse train generation happening on my ni usb-6211... using FREQ OUT, using a divisor on this, and routing it to PFI4.
id like to update my VI so i can specify the number of pulses....
im pretty much a noob at this stuff so any help would be greatly appreciated!! thanks!
dan
Attachments:
pulse train generation.vi ‏25 KB

Hi,
No problem at all, we are here to help. What I’m going to do first is to point you to a bunch of examples for that might give you a better insight of the capabilities of the card in terms of finite pulse generation. What you should be looking at is called retriggerable pulse generation and here are some examples to look at: Retriggerable Finite Pause Trigger Digital Pulse Train Generation, Creating a Delayed, Retriggerable and Finite Pulse Generator, DAQmx - Retriggerable Pulse Train Generation - LabVIEW - CVI - ANSI C - VB.NET - C#.NET and Retriggerable Finite Pulse Train with Changing Pulse Specs.
Let me know it helps
Jaime Hoffiz
National Instruments
Product Expert
Digital Multimeters and LCR Meters

Loss of Synchronization for Finite Pulse Train generation

I have successfully generated a finite pulse train on my 6608. My program is based off an example I got from NI Zone (Square_Wave_Trigger.zip).
Unfortunately, the Finite Pulse Train loses synchronization every once in a while, and I'm not sure why. Is there anyway to prevent the loss of synchronization???
When I say loss of synchronization, here is what I mean exactly. I'm generating 4 pulses, but every once in a while, when I reprogram my equipment, I lose those 4 pulses. They seem to go out of phase or something.
I have included my code as well (Sync.txt), which is slightly different from the example code. In my code, the finite pulse train is generated by the "Sequence Gating Pulse"
and the "USIP Firing Sequence" lines of code, which are clearly marked.
Any help would be greatly appreciated. =)
Attachments:
Sync.txt ‏14 KB
TIOgenSquareWaveStartTrig.C ‏6 KB

I lose the pulse train until I reset my counters. The pulse train shifts out of phase with the main pulse. It's easier to see in the pictures below.
Attachments:
Good_Pulses.jpg ‏203 KB
Shifted_Pulses.jpg ‏220 KB

PXI 6602 - Retriggerable Finite Pulse Train Generation

Hi,
I have a VI in LV7.1 where I configure PXI 6602 to generate finite pulses whenever a trigger is received. And the Retriggerable Property is set to TRUE. I look for the task to complete in order to proceed with the other operations.. This actually works. As soon as the pulses are generated DAQmx Task Done becomes TRUE.
The same VI I upgraded to LV 2011but this time the 'DAQmx Task Done?' never becomes TRUE even after the trigger is received and pulses are generated.
Does anyone know if the 'DAQmx Task Done?' functionality is changed in higher version of LabVIEW so that it no more works as it was in LV 7.1?
Is yes, then do you know what property to use to know that the operation is done?
Any help is highly appreciated.
Thanks.

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

Pulse train generation fails with certain values for "number of samples"

I'm generating a retriggerable analog output signal, and so I'm using a counter as the sample clock (see: Retriggerable AI Using Retriggerable Counter). I am finding that, above a certain number of samples, and only for certain values of the number of samples, the counter task gives me error -200305, "Desired finite pulse train generation is not possibe." The error crops up only when actually starting the task.
The analog signal that I'm trying to generate will be about 800 kHz, so my counter is set to run at the same frequency. I find that the counter task works fine if the number of samples to generate is anywhere between zero and 671,088 samples. Setting the number of samples to 671,089 gives the error above, as does 671,090 samples and so on. However, using 671,096, the counter task works fine. After that, the counter seems to output fine only if the number of samples is divisible by 8.
The only thing I can think of is that (617088 samples) / (800000 Hz) = 0.839 s. At the internal clock rate of 20 MHz, 0.839 s is 2^24 samples, and it is a 24-bit counter on this hardware. So if it's this internal counter rolling over, that's fine and I can work around that. But if that's the case, what I don't understand is why increasing the number of samples in increments of 8 samples still works.
The hardware is a PXI-6733 board, running with LabView 7.1.1 and NI-DAQmx 8.1.

Hmmm, multiples of 50 & 100? Now I'm puzzled again.
Here's how to make sense of the 100 kHz timebase idea though, even if it turns out not to be the right explanation. For a retriggerable finite pulse train, you actually use a pair of counters. If you were to program it manually, you could set your output counter to generate a continuous pulsetrain at 800 kHz using the internal 20 MHz timebase. This output counter would also be configured to use the other counter's output as a digital level-based pause trigger. So the 800 kHz pulsetrain is only output while the other counter's output is, say, high.
The other counter is configured for retriggerable pulse generation. The pulse duration or high time should be set for (# pulses) / (800e3 pulses/sec). This other counter can be configured to use the 100 kHz timebase, so its high time would then have to be an integer multiple of 10 usec.
So let's see... An 800 kHz pulsetrain is possible with a 20 MHz timebase (exactly 25 cycles). A 700 kHz (28 + 4/7 cycles) or 900 kHz (22 + 2/9 cycles) is not. So when you request those other frequencies, you actually get a near approximation. I dunno if DAQmx can be queried for the actual value correctly or not -- I recall an early version that reported back whatever freq you had asked for rather than what it actually used. Queries based on ticks (rather than time or freq) did return what was actually used, as I recall.
Let's suppose a request for 700 kHz gets truncated to 28 cycles of the 20 MHz timebase making a 1.4 usec period. Then 50 of those periods becomes 70 usec, which is evenly divisible by the 100 kHz timebase. Bingo! (Note: 70 is the least common multiple of 10 and 1.4)
Now suppose the request for 900 kHz turns into 22 cycles of the 20 MHz timebase, or a 1.1 usec period. Now it takes 100 of those periods to get to 110 usec, which is also evenly divisible by the 100 kHz timebase. Bingo again! (Note: 110 is the lcm of 10 and 1.1).
Did you follow the method here? It should help you figure out expected results for various output freqs and #'s of samples.
-Kevin P.

How to change the frequency of a finite pulse train?

Hi all? I Know I’ve asked once a similar question, but I need a better answer. I would like some ideas or examples on how to modify the example in LV; "Finite Pulse Train Generation - Intermediate for AM9513-Based Devices",so that the frequency can be changed while the VI is executing.
Will i have any problem with I use this VI in a DAQ-STC-Based Devices(E-series)?

Tiano,
I will try to better explain the paragraph on LabVIEW. The original paragraph reads ...
"While in a loop for continuous pulse train generation, make two calls to Counter Set Attribute.vi to set the values for "pulse spec 1" (constant 14) and "pulse spec 2" (constant 15). Following these calls you would make a call to Counter Control.vi with the control code set to "switch cycle" (constant 7). The attached LabVIEW programs demonstrate this flow."
You can make two calls to Counter Set Attribute or you can make a call to Set Pulse Specs which, if you open this VI, you will see that it is just making two calls to Counter Set Attribute. What you are doing with the Counter Set Attribute VIs is setting two registers called "pulse s
pec 1" and "pulse spec 2". These two registers are used to configure the frequency and duty cycle of your output frequency.
The example program which is attached to this Knowledge Base demonstrates how to change the frequency of a continuous generation on the fly. Why continuous? Because changing the frequency of a finite train would be easy. When the train completes it's finite generation you would just change the frequency and run a finite train again. You would not care about the time delay due to reconfiguration of the counter.
If you would like to change the frequency of the pulse train using a knob, this functionality will have to be added in the while loop. The while loop will be continuously checking for the new value of the knob and using the knob value to set the pulse specs.
LabVIEW is a language, and as with learning all new languages (spoken or programatic) there is a lot of learning to be accomplished. The great thing is that LabVIEW is much easier than mo
st languages and the learning curve should be much smaller. Don't fret, you'll be an expert before you know it. Especially since you're tackling a challenging first project.
Regards,
Justin Britten

Question of pulse train generation

Hi,
      I need to change the frequency of a continuous pulse train to control a stepper motor.
All examples I found is to update the parameters of a counter in a while loop. How fast
the frequency can be updated depends on the execution time of the loop. Most examples
have a 10ms delay function in the loop. I want to update the frequency in 0.01ms interval,
I wonder if is it possible to use this method. Is there a better way to do it?
      Thanks for help!
      Regards,
      Tao

Tao,
Unfortunately, you're not going to be able to update your frequency at a rate of 0.01 msec (100 kHz) for at least two reasons.
1. If you're using Windows, the OS won't loop at a consistent rate. The variations wil easily be in the order of milliseconds, possibly more.
2. The counter hw won't allow you to change a frequency until a full pulse has been generated at the prior frequency. You couldn't change the freq at 100 kHz unless the step rate was in the 100's of kHz.
I've been waiting for NI to provide NI-DAQ support for buffered pulse generation for about 7 years now, largely for the kind of stepper control you're describing. At this point, I've stopped holding my breath...
Meanwhile, there may be some other options. You could consider a dedicated motion control card. Or you could use a card supporting timed DIO (such as the new M-series cards). Finally, here's a link to an example I worked up that allows you to generate a finite pulse train with varying frequency. It isn't everything you need, but it might be a nudge in a useful direction...
http://forums.ni.com/ni/board/message?board.id=40&message.id=2411#M2411
-Kevin P.

Two retriggerable pulse generations after a pulse train generation

I am trying to generate 3 pulse trains (ABCABCABC...) one after another.
The program currently I am using generates 2 pulse trains (ABABAB.....).
I am using the Traditional NI-DAQ and PCI-6602.
I am thinking about using pulse train generation first and then retriggerable pulse generation after that.
I understand that the retriggerable pulse generation can generate a pulse train triggered (or gated) by other counter output.
I have attached a test vi.
It uses the pulse train generation code when the counter number is 0 and when the counter number is not 0, then it uses the retriggerable pulse generation code, which I tried to modify from the pulse train generation code.
First of all, I am not sure if I wrote the retriggerable pulse generation code correctly.
Secondly, I don't know if the whole code will generate ABCABCABC...
I would really appreciate your help.
pchemjjang

pchemjjang,
I believe I may have misunderstood your original concern. It sounds like you want to output this finite pulse train on three different counters. You will output these pulse trains for 10 minutes and cease your program. The Finite Pulse Train.vi will output a pulse train from only one counter. With this Traditional DAQ example you would need to have three of these Finite Pulse Train.vi programs running simultaneously in parallel to output from 3 counters. I would strongly recommend using DAQmx for this application because you will only need to utilize 4 VIs. The rest of the work is done behind the scenes. There is an example in DAQmx which should accomplish exactly what you are looking for in one program. You must make sure to make the number of pulses 2000000, the duty cycle as 1/3 and the frequency as 1/(300us). The DAQmx driver can found here. In terms of the counters, I believe that each task requiring two counters will use the counter adjacent to it. If you would like to output on counter 0 using finite generation then counter 1 will be used as the gating counter. When you have the DAQmx driver then you can find this example by selecting Help>>Find Examples and then expanding Hardware Input and Output>>DAQmx>>Generating Digital Pulses>>Gen Dig Pulse Train-Finite.vi. I have included an image to show how the front panel of this example should be configured to work. The major note to make is that you will need to configure all of the counters in the channel names list. In Traditional DAQ this did not seem possible. In Traditional DAQ you would need to create a subvi out of the Finite Pulse Train.vi run three copies of it, in parallel, in a larger program. Please let me know if you will be able to utilize DAQmx in this application.
Thanks,
Gio L.
Digital Support - Product Manager
National Instruments
Attachments:
Counteroutput.jpg ‏49 KB

Finite Pulse Train

Dear All,
I have an application where I am using digital finite pulses (see attached example) but I want the generation to be stopped by the user too in addition to the task completed function.
Also, when I use generate finite pulse / generate continuous pulses can I use the other counter to count the pulses.
I am using PCI 6221 & LV8.0
Regards
James
Attachments:
FINITE PULSE TRAIN.vi ‏26 KB

Hello james!
Thanks for your post. I think what you want to do instead of "wait until DAQmx task is done" just use the "is DAQmx tasks done". That way you only call the VI once in software and it either returns true or false. If you "wait" until the task is done then you program loop will not continue until the task is finished. Take a look at the following pictures that shows you how I would do it. The task will give you a warning and tell you that you have not finished generating all the pulses yet but its just a warning and the task will stop. Let me know if you have any other questions and if this helps you with your application.
Cheers!
Corby_B
http://www.ni.com/support
Attachments:
False case keep generating.JPG ‏44 KB
True case STOP program.JPG ‏43 KB

Finite Pulse Train TIO-Timing Specs

Howdy everyone,
Got a question regarding the pulse specs of finite pulse generation with a 6602 (TIO chip).
I'm using a slightly modified version of the Finite Pulse Train (NI_TIO).vi found in the examples directory to produce finite pulses.
The slight modifications are to allow for some hardware triggering. I am using counters 2 and 3 to produce a finite pulse train.
My external electronics provides the trigger to the gating counter.
I want all of my timing specs relative to this external pulse.
Let's say I want a delay of 10 seconds until my first output pulse is produced by the output counter; I want pulses to come every 1 sec; Pulses are 0.5 sec wide.
I know from looking into the VI's that the TOTAL delay--ie the time from my external trigger until the time the output counter outputs a 0.5 sec pulse--is equal to the "initial delay (in secs) in the finite pulse specs cluster in the VI plus the interpulse interval minus the pulse width.
Thus, If I enter a value of 10 seconds for initial delay, I actually expect the first pulse to be output at time = 10 +1 - 0.5 sec = 10.5 sec. This is one-half second later than desired, but it is easy to correct.
Now for my real question:
I'm usually looking at pulses coming about 20 msec after the trigger arrives. The pulse interval is 5msec and the pulses are 0.5 msec wide.
Even when I program my counters to get the timing I want with this correction, ie. implement the formula Desired Delay = "Initial Delay" - (pulse interval - pulse width), I still see my pulse arriving late by 1msec. 1 msec is enough that I care to get it right. I don't understand the source of this delay. Does anyone have any idea what could be happening?
It seems totally independent of any parameters I enter for pulse interval, intial delay, pulse width.
Not sure if it matter, but I'm generating this finite pulse train inside of a much larger VI that is busy collecting and displaying data from a 6071E.
Any thoughts/help would be greatly appreciated!

I'm using Traditional DAQ (not DAQmx), so I think points 3 and 4 are not strictly true for my VI.
(I'm am very hesitant at this moment to think about switching over to DAQmx : I"m at the end of my graduate career and don't have the time to overhaul my program at the moment; and my VI works perfectly for my needs..except the 1msec delay. I'll suggest future lab peoples move to mx...)
As I understand, for traditional DAQ:
1. Start the counter -- I believe it will force the output into its idle state (low by default).
2. Trigger edge occurs
3. Output remains in idle state for "initial delay."
4. Output transitions to armed state and remains low for "low time" which is computed/specified by the "frequency" and "duty cycle" specs. So the total delay is the "initial delay" + "low time"
5. Ouput transitions to high state for a time, also determined/computed by the frequency and duty cycle specs.
6.Thereafter, the times will be based on your regular pulse specs, such as low time / high time.
OK, I didn't want to drag the VI into it, but it seems there is no other way; and I really want to know why my timing is not quite as I would expect.
The VI I posted has 3 outter sequence frames. The action, as far as we're concerned in this post, is in outter frame number 3; inner frame number 3, case True, subVI Finite Pulse Train (NI-TIO)-jev4.vi. This VI is "slightly" modified from the example that came packaged with LV "Finite Pulse Train (NI-TIO).vi" The modifcations I made were 1. removed the while loop that checked the status of the counters, because I needed this subVI to return before the pulse train had actually finished executing. 2. Added start trig capability to the gating counter's gate. (Maybe this is the source of the 1msec error?).
There is a variable "stim delay (msec)" that specifies when the first high pulse should be output from the 6602. (device 2 for me.)
To complicate things further, " stim delay" is actually relative to another variable in Neurochip-legacy.vi called "record delay." Record delay specifies the delay between the the arrival of the trigger pulse and start of data acquisition on NI6071E. (had to do this because of the way things are set up in the lab). This trigger pulse is shared with the 6602--it is hardwired in a breakout box to also be routed to my 6602 card. Thus, if the trigger arrives at time = 0, record delay = 20 msec, and stim delay = 40 msec, I would like to see my first output pulse of the train (on the 6602) come at time = 60 msec.
For the time being I have set the "initial delay" = record delay + stim delay - (pulse interval - Ta), where pulse interval is just 1/"frequency" parameter for finite pulse generation, and Ta is the desired width of the output pulse which in turn specifies "duty cycle" parameter. For the moment, I've also hardcoded in a 1msec correction--which was the whole reason for the original post.
Maybe in all this arithmetic and wiring I've made a goof somewhere...if so, maybe a fresh pair of eyes would help.
Ok, so if you are brave enough to check out the code, it is attached.
If you find that you are getting the same result as me, I would love to know it.
If you are getting different result than me, I'd love to know it.
If you see where I went wrong, I'd really love to know where.
Thanks very much
jon
Attachments:
Neurochip-Legacy.vi.zip ‏637 KB

Finite pulse train with different frequency

Hello,
I'm trying to modify the labview example "generate finite pulse train" to generate a finite pluse train with different frequencies. Each freq will run 400 pulses. The freqs are stored in an array, which is being fed into a for loop. Thus ramp up the freq each iteration. However the program only generate 400 pluse at first given freq. I'm fairly new to daqmx and not sure what is wrong. Anyone have some idea how to fix it?
Attachments:
pulse train finite mod.vi ‏38 KB

The best "fix" will depend a bit on the needs of your app.
Is it ok to have a fraction of a second without any pulses each time you change frequencies? If so, then there's a pretty simple solution:
1. Outside the loop you'd create a DAQmx virtual channel and configure for Finite Sampling (# samples = 400) using DAQmx Timing.vi.
2. Inside the loop you'd chain together a DAQmx Channel property node where you set the pulse frequency property, then perform a DAQmx Start, a DAQmx "Wait for Task Complete", and a DAQmx Stop.
3. So for each freq in your array, you'll program the counter for that frequency, start the generation of pulsetrains, and then stop the task after 400 pulses have been generated.
If you must change frequency on-the-fly, producing *exactly* 400 pulses at each freq setpoint will be tricky, and maybe even impossible to do reliably.  Some techniques will get you closer than others though, so post back if you need to do this.
-Kevin P.

How do I generate two finite pulse trains using counters on PXI-6251

I'm trying to use Counter 0 and Counter 1 on the PXI-6251 to generate two finite pulse trains. But, I get this error: "The specified resource is reserved. The operation could not be completed as specified." See attached example.
Inside the disabled box is what I'd like to run on both counters. I stripped things down to creating the task, starting, and stopping. I then started to add things to see what my problem was. The timing VI seems to be what causes me issues but I don't know why.
My end objective is two identical pulse trains with one delayed by 5us, which I figured would be easy to do in the initial delay. I tried both in a single task and as separate tasks with no avail.
Attachments:
2_counter_outputs.vi ‏32 KB

Hi SirMutt,
Creating a finite pulse train requires
two counters. What’s really happening is that one counter is creating a
continuous pulse train while the other counter applies a finite pulse to “window”
the pulse.
What you want to do is correlated DIO. I’ve
done a search on our website for “correlated DIO” and have come up with a few
resources. Hopefully that will help you get started.
Digital Output and Pulse Generation
Performing Correlated Digital IO with an M Series Device in LabVIEW
M Series Hardware-Time DIO with Counter Clock Generation
Mark E.
Precision DC Product Support Engineer
National Instruments
Digital Multimeters (DMMs) and LCR Meters
Programmable Power Supplies and Source Measure Units

Delayed retriggerable finite pulse train

Hi there,
I'm trying to create a delayed retriggerable finite pulse train on a USB-6251 (2 counters). I just read an old thread on this problem and I got it to work.
However, I'm having this one small annoying issue:
I want to send a finite pulse train (3 pulses) at 1Hz
The trigger has a period of 3seconds (0.333333Hz)
My initial delay is 0.1s
This results in the following :
first 3 seconds : perfect 0.1s delay, 3 pulses at 1Hz
second 3 sec : nothing
third 3 sec : perfect 0.1s delay, 3 pulses at 1Hz
and so on
I reckon this is because the counter that is gating the continuous pulses is not finished yet with his pulse and therefore does not "see" the new rising edge of the trigger.
Is there a way I could solve this?
I know I could just use the first trigger and send 150 pulses or so at 1Hz. That's what I would do if I was very confident in the accuracy of the 3s period of the trigger, but I'm not. And since it is very important the timing is accurate after that trigger, I think I will induce to much error in the timing that way.
Any ideas?
Cheers,
Tom

Sorry for boosting this thread, but I just noticed something in the program Alan suggested : Delayed_Retriggerable_Finite_Pulse_Train.vi while checking its output on a scope:
If you set an initial delay, the pulse train actually starts after 2 times that delay time after the initial trigger. I can't seem to find where this factor 2 is coming from.

Retriggerable finite pulse train

I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continueous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on between pulse trains, when it should be turned off. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. I use the ActualPeriod of the first re-triggerable pulse to ensure the pulse train ends correctly within window of the first re-triggerable pulse, but it seem to wander. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem. I may have to use a single re-triggerable pulse instead of a re-triggerable pulse train as this work correctly every time. However, multiple pulses creates a finer mist from a fuel injector and is the correct why to modulate a fuel injector. The

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

Finite pulse train generation?

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