Two retriggerable pulse generations after a pulse train generation

I am trying to generate 3 pulse trains (ABCABCABC...) one after another.
The program currently I am using generates 2 pulse trains (ABABAB.....).
I am using the Traditional NI-DAQ and PCI-6602.
I am thinking about using pulse train generation first and then retriggerable pulse generation after that.
I understand that the retriggerable pulse generation can generate a pulse train triggered (or gated) by other counter output.
I have attached a test vi.
It uses the pulse train generation code when the counter number is 0 and when the counter number is not 0, then it uses the retriggerable pulse generation code, which I tried to modify from the pulse train generation code.
First of all, I am not sure if I wrote the retriggerable pulse generation code correctly.
Secondly, I don't know if the whole code will generate ABCABCABC...
I would really appreciate your help.
pchemjjang

pchemjjang,
I believe I may have misunderstood your original concern. It sounds like you want to output this finite pulse train on three different counters. You will output these pulse trains for 10 minutes and cease your program. The Finite Pulse Train.vi will output a pulse train from only one counter. With this Traditional DAQ example you would need to have three of these Finite Pulse Train.vi programs running simultaneously in parallel to output from 3 counters. I would strongly recommend using DAQmx for this application because you will only need to utilize 4 VIs. The rest of the work is done behind the scenes. There is an example in DAQmx which should accomplish exactly what you are looking for in one program. You must make sure to make the number of pulses 2000000, the duty cycle as 1/3 and the frequency as 1/(300us). The DAQmx driver can found here. In terms of the counters, I believe that each task requiring two counters will use the counter adjacent to it. If you would like to output on counter 0 using finite generation then counter 1 will be used as the gating counter. When you have the DAQmx driver then you can find this example by selecting Help>>Find Examples and then expanding Hardware Input and Output>>DAQmx>>Generating Digital Pulses>>Gen Dig Pulse Train-Finite.vi. I have included an image to show how the front panel of this example should be configured to work. The major note to make is that you will need to configure all of the counters in the channel names list. In Traditional DAQ this did not seem possible. In Traditional DAQ you would need to create a subvi out of the Finite Pulse Train.vi run three copies of it, in parallel, in a larger program. Please let me know if you will be able to utilize DAQmx in this application.
Thanks,
Gio L.
Digital Support - Product Manager
National Instruments
Attachments:
Counteroutput.jpg ‏49 KB

Similar Messages

How do I generate two finite pulse trains using counters on PXI-6251

I'm trying to use Counter 0 and Counter 1 on the PXI-6251 to generate two finite pulse trains. But, I get this error: "The specified resource is reserved. The operation could not be completed as specified." See attached example.
Inside the disabled box is what I'd like to run on both counters. I stripped things down to creating the task, starting, and stopping. I then started to add things to see what my problem was. The timing VI seems to be what causes me issues but I don't know why.
My end objective is two identical pulse trains with one delayed by 5us, which I figured would be easy to do in the initial delay. I tried both in a single task and as separate tasks with no avail.
Attachments:
2_counter_outputs.vi ‏32 KB

Hi SirMutt,
Creating a finite pulse train requires
two counters. What’s really happening is that one counter is creating a
continuous pulse train while the other counter applies a finite pulse to “window”
the pulse.
What you want to do is correlated DIO. I’ve
done a search on our website for “correlated DIO” and have come up with a few
resources. Hopefully that will help you get started.
Digital Output and Pulse Generation
Performing Correlated Digital IO with an M Series Device in LabVIEW
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Can I use two "finite pulse train" to work in parallell with different freq.?

I want to generate two seperate pulsetrains in parallell with different freq. and number of pulses. I am using a "PCI 6036E" with two counters on the device. I think I need four counters to make this task? I would be very glad if anyone had any answer on this

It will take four counters to generate two pulse trains with two different frequencies and number of pulses. As a workaround with your existing device, you can possible create a pulse train using one of the analog outputs, if it's available. Otherwise, you'll need either another MIO device or you could choose to use a TIO device (660x) which will have 4-8 counters.
Hope this helps!
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Trigged generation of two pulse trains

I have to write an application that will generate two equal pulse trains (with a given phase difference) on two different counters when I recieve a trigger signal. I'm using a 6063daq-card. If anyone have an related example, or some hint on how to solve this (elementary problem) please let me know.

Hi OG,
Although this functionality is present on NI-TIO counter/timer chips (NI-660x boards) by use of an initial delay within the counters (could program a delay equal to the desired phase shift) this is not available on DAQ-STC chips (E Series boards). This is because DAQ-STC counters do not support an initial delay in pulse train generation mode (driver doesn't support it).
The only way I see this happening is if you use the frequency generator on the E Series to generate your first pulse train (output on the freq_out pin) and use your two main counters to generate 1) a triggered and delayed pulse which will gate 2) your second counter which is a pulse train of the same frequency. To get the phase correct, your delay of the pulse should be equal to t
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How Can I Generate Two Pulse Trains without Using Both Counters on My E-series Data Acquisition Board?
http://digital.ni.com/public.nsf/ websearch/ 129541C85CEEDDBF86256ADF005C4409?OpenDoc ument
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http://digital.ni.com/public.nsf/ websearch/ B8A49A4E33F38AB686256B610061DC6D?OpenDoc ument
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Finite pulse train generation... how to count number of pulses?

hi guys,
this has probably been solved a hundred times but i just couldnt find it!!
i have a pulse train generation happening on my ni usb-6211... using FREQ OUT, using a divisor on this, and routing it to PFI4.
id like to update my VI so i can specify the number of pulses....
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Attachments:
pulse train generation.vi ‏25 KB

Hi,
No problem at all, we are here to help. What I’m going to do first is to point you to a bunch of examples for that might give you a better insight of the capabilities of the card in terms of finite pulse generation. What you should be looking at is called retriggerable pulse generation and here are some examples to look at: Retriggerable Finite Pause Trigger Digital Pulse Train Generation, Creating a Delayed, Retriggerable and Finite Pulse Generator, DAQmx - Retriggerable Pulse Train Generation - LabVIEW - CVI - ANSI C - VB.NET - C#.NET and Retriggerable Finite Pulse Train with Changing Pulse Specs.
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I am trying to generate two different pulse trains. Once the first pulse train has begun I need to start the
second pulse train approximately .69444 ms after the first has started. I am currently using the two counter channels on the NI ELVIS, but the second pulse doesn't always start after the first, but it does work sometimes. How can I fix this? Attached is my vi file.
Thanks,
David
Note: Each pulse train has a 33% duty cycle.
Attachments:
SaO2.vi ‏91 KB

Hello,
Here is what I would try:
1. Set up counter 0 to perform a continuous pulse train (see the LabVIEW example called Gen Dig Pulse Train-Continuous.vi)
2. Set up counter 1 to perform a continuous pulse train with a digital start (see the LabVIEW example Gen Dig Pulse Train-Continuous-Dig Start.vi)
A. Modify this example code so that the trigger source is your counter 0 output.
B. Modify this example code so that the initial delay value of the pulse train is 0.7 milliseconds (or whatever delay you want). Create the delay with the input to the DAQmx Create Channel VI (the delay is currently set with a default of 0.00 seconds).
What you are doing is triggering the second counter off of the rising edge of the first counter. So, counter 0 will start generating a pulse train. Counter 1 will not start until the rising edge of counter 0's first pulse has occurred. Once this trigger has occurred, Counter 1 will start (after the initial delay time of 0.7 ms has passed). You can cut and paste to put the code of the two examples together.
Hope this works for you,
Sam

Can daq 6035e,or 6024e used to count pulse train

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Hi,
Both of those DAQ boards can measure digital pulse train frequencies using the counters. These cards can support 2-pulse encoder measurements on DIO6 and DIO7. This means that if there is a rising edge on Channel A the counter increments and a rising edge on Channel B decrements the count. You can also set the counter application for frequency measurement and that will measure the frequency of the pulse train on the line. These cards also have 2 such counters.
There are many LabVIEW and CVI examples demonstrating this. If you search the site for position or encoder measurements there should be some example programs for you. Hope that helps.
Ron

PXI 6602 - Retriggerable Finite Pulse Train Generation

Hi,
I have a VI in LV7.1 where I configure PXI 6602 to generate finite pulses whenever a trigger is received. And the Retriggerable Property is set to TRUE. I look for the task to complete in order to proceed with the other operations.. This actually works. As soon as the pulses are generated DAQmx Task Done becomes TRUE.
The same VI I upgraded to LV 2011but this time the 'DAQmx Task Done?' never becomes TRUE even after the trigger is received and pulses are generated.
Does anyone know if the 'DAQmx Task Done?' functionality is changed in higher version of LabVIEW so that it no more works as it was in LV 7.1?
Is yes, then do you know what property to use to know that the operation is done?
Any help is highly appreciated.
Thanks.

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

Gen Digital Pulse Train Finite Retriggerable - Initial Delay is only for first trigger

The DAQmx example Gen Digital Pulse Train Finite Retriggerable has an Initial Delay parameter. It appears (6602 and an E series card) that this Initial Delay only delays the pulse generation for the first trigger. Subsequent triggers show no delay. Is this the designed behavior ? Any way to get the Initial Delay to occur for all triggers ?
Steve

So, yes, you are seeing the appropriate behavior. However, it is possible to get a re-triggerable finite pulse train with an initial delay. What you have to do is set up a re-triggerable pulse, and have that pulse act as a pause trigger for a continuous pulse train. Let me explain further with an example.
1) Set up counter 0 as a re-triggerable single pulse (Gen Dig Pulse-Retriggerable.vi). Set the low time = initial delay = X, and high time = Y. The re-triggerable pulse will be low for X, then high for Y after every trigger (it applies the initial delay to the first pulse, and the low time to every pulse after the first). The trigger source is your actual trigger.
2) Set up counter 1 as a pause-triggered continuous pulse train (Gen Dig Pulse Train-Continuous-Pause Trigger.vi). This pulse train will be the frequency of the finite pulse train you want. The pause trigger source will be the output of counter 0.
I have attached the VIs I used to accomplish this. There are three VIs, the two mentioned in 1) and 2) and another VI I used just to monitor the signals. These could be combined to a single VI if you would like. Hope this helps!
-Alan A.
Attachments:
Retrig_Finite_Pulse_Delay.zip ‏135 KB

Pulse train generation fails with certain values for "number of samples"

I'm generating a retriggerable analog output signal, and so I'm using a counter as the sample clock (see: Retriggerable AI Using Retriggerable Counter). I am finding that, above a certain number of samples, and only for certain values of the number of samples, the counter task gives me error -200305, "Desired finite pulse train generation is not possibe." The error crops up only when actually starting the task.
The analog signal that I'm trying to generate will be about 800 kHz, so my counter is set to run at the same frequency. I find that the counter task works fine if the number of samples to generate is anywhere between zero and 671,088 samples. Setting the number of samples to 671,089 gives the error above, as does 671,090 samples and so on. However, using 671,096, the counter task works fine. After that, the counter seems to output fine only if the number of samples is divisible by 8.
The only thing I can think of is that (617088 samples) / (800000 Hz) = 0.839 s. At the internal clock rate of 20 MHz, 0.839 s is 2^24 samples, and it is a 24-bit counter on this hardware. So if it's this internal counter rolling over, that's fine and I can work around that. But if that's the case, what I don't understand is why increasing the number of samples in increments of 8 samples still works.
The hardware is a PXI-6733 board, running with LabView 7.1.1 and NI-DAQmx 8.1.

Hmmm, multiples of 50 & 100? Now I'm puzzled again.
Here's how to make sense of the 100 kHz timebase idea though, even if it turns out not to be the right explanation. For a retriggerable finite pulse train, you actually use a pair of counters. If you were to program it manually, you could set your output counter to generate a continuous pulsetrain at 800 kHz using the internal 20 MHz timebase. This output counter would also be configured to use the other counter's output as a digital level-based pause trigger. So the 800 kHz pulsetrain is only output while the other counter's output is, say, high.
The other counter is configured for retriggerable pulse generation. The pulse duration or high time should be set for (# pulses) / (800e3 pulses/sec). This other counter can be configured to use the 100 kHz timebase, so its high time would then have to be an integer multiple of 10 usec.
So let's see... An 800 kHz pulsetrain is possible with a 20 MHz timebase (exactly 25 cycles). A 700 kHz (28 + 4/7 cycles) or 900 kHz (22 + 2/9 cycles) is not. So when you request those other frequencies, you actually get a near approximation. I dunno if DAQmx can be queried for the actual value correctly or not -- I recall an early version that reported back whatever freq you had asked for rather than what it actually used. Queries based on ticks (rather than time or freq) did return what was actually used, as I recall.
Let's suppose a request for 700 kHz gets truncated to 28 cycles of the 20 MHz timebase making a 1.4 usec period. Then 50 of those periods becomes 70 usec, which is evenly divisible by the 100 kHz timebase. Bingo! (Note: 70 is the least common multiple of 10 and 1.4)
Now suppose the request for 900 kHz turns into 22 cycles of the 20 MHz timebase, or a 1.1 usec period. Now it takes 100 of those periods to get to 110 usec, which is also evenly divisible by the 100 kHz timebase. Bingo again! (Note: 110 is the lcm of 10 and 1.1).
Did you follow the method here? It should help you figure out expected results for various output freqs and #'s of samples.
-Kevin P.

Finite pulse train generation?

i am trying to generate a very specific pulse with my tio-6602 in labwindows. after a 20us delay, i want the board to generate 20 pulses, with a width of 1 us and an interval of 5us. ideally, this would be retriggerable at 100 Hz. any suggestions on what would be the best way to approach this problem?

Paco,
You can use a gated pulse train, which is similar to finite pulse train generation. With finite pulse train generation, you have one pulse for the gate of a counter set to generate a pulse train. The pulse train will only be output based on the gate, so if one pulse appears, you have a finite pulse train. Now, if you make the gate be a pulse train itself, then you can continuously output bursts of pulses. For instance, you can set it up such that the pulses are output when the gate is high. When the gate is low, the counter pulses would pause and when the gate resumes to the high states, your pulses would continue. I've attached a code excerpt for using NI-DAQ function calls to generate a finite pulse train that is in our database. I will see abo
ut getting it put onto the http://www.ni.com/support pages. You can also find more information about the function calls used by referencing the NI-DAQ Help file installed with the NI-DAQ driver software and with the NI-DAQ User Manual, which is available at the web pages.
Regards,
Geneva L.
Applications Engineering
National Instruments
http://www.ni.com/ask
Attachments:
finitepulsetrain.txt ‏2 KB

Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
My question is, Is there any way to do the finite pulse train generation, unreserve the counters, wait for a finite count to finish and so on?
Thanks.

Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
However, the finite pulse train generation and the continuous pulse train generation seem similar. The key difference is the generation mode from continuous to finite and the use fo a DAQmx Wait Until Done vi instead of a loop to monitor user input. From a point of view of the hardware there is a difference between the two. Continuous pulse train generation requires only 1 COUNTER.
Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

Question of pulse train generation

Hi,
      I need to change the frequency of a continuous pulse train to control a stepper motor.
All examples I found is to update the parameters of a counter in a while loop. How fast
the frequency can be updated depends on the execution time of the loop. Most examples
have a 10ms delay function in the loop. I want to update the frequency in 0.01ms interval,
I wonder if is it possible to use this method. Is there a better way to do it?
      Thanks for help!
      Regards,
      Tao

Tao,
Unfortunately, you're not going to be able to update your frequency at a rate of 0.01 msec (100 kHz) for at least two reasons.
1. If you're using Windows, the OS won't loop at a consistent rate. The variations wil easily be in the order of milliseconds, possibly more.
2. The counter hw won't allow you to change a frequency until a full pulse has been generated at the prior frequency. You couldn't change the freq at 100 kHz unless the step rate was in the 100's of kHz.
I've been waiting for NI to provide NI-DAQ support for buffered pulse generation for about 7 years now, largely for the kind of stepper control you're describing. At this point, I've stopped holding my breath...
Meanwhile, there may be some other options. You could consider a dedicated motion control card. Or you could use a card supporting timed DIO (such as the new M-series cards). Finally, here's a link to an example I worked up that allows you to generate a finite pulse train with varying frequency. It isn't everything you need, but it might be a nudge in a useful direction...
http://forums.ni.com/ni/board/message?board.id=40&message.id=2411#M2411
-Kevin P.

Continuous pulse train generation on my PCI 6602 takes up too much of my system resources.

I am using a PCI 6602 to generate a clock signal that is to synchronize pattern generation on two PCI 6534's. I have done this by generating a pulse train at a user defined frequency on the PCI 6602. My problem is when I generate this pulse train, the program uses all of the computer's CPU, and slows the rest of the processes down. Just to let you know, I have isolated this program to ensure it is the only thing running, and it still has the same result. The CPU usage soars to 100%(and remains constant) and the memory consumption increases (and remains constant) as well. Also, if it helps at all, the CPU consumption is completely independent of the frequency that is being gene
rated, but the memory usage increases a little with an increase in frequency. Does anyone have any insite as to how to fix this, for I have noticed that all of the posted examples like this behave in the same manner.
Thanks,
Dave

Russell,
Thanks for the reply. Just about five minutes ago I came to the realization that the card itself was not causing this to happen. When I took a closer look, I found that my C program and all of the example programs were using the NIDAQWaitForKey() function to enable countinuous generation. So what was happening was that function was constantly polling the CPU to find a key to be pressed. So lets just say I found a way around this problem, and so everything is well. There are a handfull of things that i need to work on now, but at least I know my clock generation program is correct and I can stop banging my head against a wall trying to solve a problem that does not exist and for which there is no solution.
Thanks Again,
Dave

Retriggerable finite pulse train

I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continueous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on between pulse trains, when it should be turned off. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. I use the ActualPeriod of the first re-triggerable pulse to ensure the pulse train ends correctly within window of the first re-triggerable pulse, but it seem to wander. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem. I may have to use a single re-triggerable pulse instead of a re-triggerable pulse train as this work correctly every time. However, multiple pulses creates a finer mist from a fuel injector and is the correct why to modulate a fuel injector. The

CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

Two retriggerable pulse generations after a pulse train generation

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