How do I generate two finite pulse trains using counters on PXI-6251

I'm trying to use Counter 0 and Counter 1 on the PXI-6251 to generate two finite pulse trains. But, I get this error: "The specified resource is reserved. The operation could not be completed as specified." See attached example.
Inside the disabled box is what I'd like to run on both counters. I stripped things down to creating the task, starting, and stopping. I then started to add things to see what my problem was. The timing VI seems to be what causes me issues but I don't know why.
My end objective is two identical pulse trains with one delayed by 5us, which I figured would be easy to do in the initial delay. I tried both in a single task and as separate tasks with no avail.
Attachments:
2_counter_outputs.vi ‏32 KB

Hi SirMutt,
Creating a finite pulse train requires
two counters. What’s really happening is that one counter is creating a
continuous pulse train while the other counter applies a finite pulse to “window”
the pulse.
What you want to do is correlated DIO. I’ve
done a search on our website for “correlated DIO” and have come up with a few
resources. Hopefully that will help you get started.
Digital Output and Pulse Generation
Performing Correlated Digital IO with an M Series Device in LabVIEW
M Series Hardware-Time DIO with Counter Clock Generation
Mark E.
Precision DC Product Support Engineer
National Instruments
Digital Multimeters (DMMs) and LCR Meters
Programmable Power Supplies and Source Measure Units

Similar Messages

How do you create a finite pulse train using a FP-CTR-502?

I have recently replaced my FP-PG-522 module with a FP-CTR-502 module, to achieve higher output frequencies (FP-PG-522 max output freq is 5kHz, wheras the FP-CTR-502 max output freq is 16 kHz).
I need to be able to generate a finite pulse train. Has anybody created a finite pulse train using a FP-CTR-502 module before? I have started to look into it, but my ideas so far have been complicated (compared to doing it in a PG module).
Any tips on this would be much appreciated.
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au
Solved!
Go to Solution.

I can answer this question myself!
The answer is in the *OLD* version (July 2000) of the operator's manual for the FP-CTR-502. For some reason, this has been removed from the latest version (June 2003).
See page 11 of this link for more information:
http://www.ni.com/pdf/manuals/322660a.pdf
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au

How do I output a finite pulse train through multiple counters?

Hello,
I have used LabView examples to create a VI to use with my TIO 6602 that generates a finite pulse train with varying duty cycle, frequency, number of pulse, and initial delay. I can also have it output the pulses through multiple counter channels, but all the channels have the same delay, and are output at the same time. I need each channel to have a specific delay from the first one.
In my VI, I use DAQmx to create a retriggerable finite pulse train by gating a counter with another counter. I have all the neccessary controls over the pulse train, but I can not seem to find an easy way to just copy this waveform and output delayed versions of it to other channels. The delay is very important because these signals will be used to drive ultrasound transducers in a linear array, and for the waveforms to focus at one point, the signal driving the transducers with a shorter distance from the focal point need a larger delay, so that the same waveform arrives from each transducer at the same time.
Any help with how I might do this would be much appreciated.
Thanks!

Hey Sneaky,
Here's a screenshot of the code I put together on how to use multiple counters. Also, take a look here for more information on how to sync multiple counters.
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:38 AM
-John Sullivan
Analog Engineer
Attachments:
4xcount.jpg ‏67 KB

Can I use two "finite pulse train" to work in parallell with different freq.?

I want to generate two seperate pulsetrains in parallell with different freq. and number of pulses. I am using a "PCI 6036E" with two counters on the device. I think I need four counters to make this task? I would be very glad if anyone had any answer on this

It will take four counters to generate two pulse trains with two different frequencies and number of pulses. As a workaround with your existing device, you can possible create a pulse train using one of the analog outputs, if it's available. Otherwise, you'll need either another MIO device or you could choose to use a TIO device (660x) which will have 4-8 counters.
Hope this helps!
gus....

How can I generate synchronized pulse trains with 6602?

Hi,
I would like to generate multiple pulse trains with different frequencies with the 6602 TIO card. Currently I am able to generate pulse trains with different frequencies. But is there any way to synchronize all the pulse trains? For example, I'd like to have all pulse trains with their first low-to-high at the same moment.
Thanks!
Dan

Dan,
Absolutely, the NI-TIO chip on the PCI-6602 supports a start trigger. If you configure all of the counters that are generating a pulse train to use this start trigger, they will be synchronized. The example Generate Pulse Train - Start Trig (NI-TIO).vi demonstrates this process for one counter. In LabVIEW 7, this example can be found in the following location:
Examples >> Hardware Input and Output >> Traditional DAQ >> Counters >> NI-TIO
You will need to add code for the other counters, but this example should give you the general idea. Furthermore, this example demonstrates how you can use one of the digital lines to generate the start trigger.
Good luck with your application.
Spencer S.

How do program 3 independent finite pulse train generators from 3 counter pairs

I need to drive a 3-axis piezo leadscrew friction type motor by finite train of pulses from a PCI-6602.How do I specify the counter pairs in my code with out any one counter conflicting with the others?
Bernardino Jerez Buenaobra
Senior Test and Systems Development Engineer
Test and Systems Development Group
Integrated Microelectronics Inc.- Philippines
Telephone:+632772-4941-43
Fax/Data: +632772-4944
URL: http://www.imiphil.com/our_location.html
email: [email protected]

This scheme (and the examples) works fine when you want finite generation done in sequence, but seems not to work with when they are done independently and in synchronously run in parallel fashion.
Berns B.
Bernardino Jerez Buenaobra
Senior Test and Systems Development Engineer
Test and Systems Development Group
Integrated Microelectronics Inc.- Philippines
Telephone:+632772-4941-43
Fax/Data: +632772-4944
URL: http://www.imiphil.com/our_location.html
email: [email protected]
Attachments:
Mutliaxis_test_drive_version_0.vi ‏85 KB
NF8096Exercise.vi ‏206 KB

How to generate sequence of pulse trains with DAQmx?

I need to generate a sequence of pulse trains with DAQmx (the card I have is a PXI-6229 card). As an example:
- 10'000 pulses at 20kHz every 5 seconds with an initial offset of 2 seconds (let's say 10 pulse trains in total).
If I use the CreateVirtualChannel.vi in "CO pulse ticks" mode, I can only specificy offset, high ticks and low ticks, but not that the sequence of pulses should be repeated after some time.
Now I thought that I could solve this problem if it were possible to multiply two counter outputs: the first counter would generate the pulses (continuously) whereas the second one would switch between low and high on a slower timescale in order to gate the first counter, thereby providing an initial offset and the "off" phases between the pulse trains.
Is it somehow possible to multiply two outputs with DAQmx and the card I have? Or is there another solution to the problem?
Thanks a lot in advance for any hints!

Hi dlanger,
what you want to do requires a little bit more work.
First look at the example "Gen Dig Pulse Train-Continuous.vi" from the LV example finder.
This example generates a continuous* pulse train. As you see, you need a sample clock VI for setting the sample mode.
* NOTE: Generating a finite pulse train with a M-series card requires 2 counter.
With a pause trigger (DAQmx trigger property node) you can gate the output of that counter.
Now you have to generate a gate-signal with the the 2nd counter. That means, only if Ctr1-out is high Ctr0-out outputs the 20 kHz-signal.
Maybe you have to adjust the times in my example a bit.
Unfortunately there is just one "small" problem: "let's say 10 pulse trains in total"
This is not possible, because a 3rd counter would be necessary (*).
As a workaround you can modify the while-loop that both tasks are cleared after 50s. This is not brilliant, but should work fine for you.
A more sophisticated way is to perform a correlated DIO. So you can generate custom pattern for multiple outputs.
A good example can you find here:
Retrigger and Repeat Finite Digital Pulse Train in LabVIEW
http://decibel.ni.com/content/docs/DOC-8473
or here:
Generating More Than 2 Pulse Trains Using CompactDAQ
http://decibel.ni.com/content/docs/DOC-2167
Hope this helps.
With best wishes,
Ralf N.
Attachments:
Gen Gated Dig Pulse Train-Continuous.vi ‏38 KB

Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
My question is, Is there any way to do the finite pulse train generation, unreserve the counters, wait for a finite count to finish and so on?
Thanks.

Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
However, the finite pulse train generation and the continuous pulse train generation seem similar. The key difference is the generation mode from continuous to finite and the use fo a DAQmx Wait Until Done vi instead of a loop to monitor user input. From a point of view of the hardware there is a difference between the two. Continuous pulse train generation requires only 1 COUNTER.
Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

Finite pulse train, stop and count

Hi, i'm using Labview 8.2 with a DaqCard-6063E on Windows Vista. I generate a finite pulse train with a possibility to stop when ever I want, but how do I do to count the number of pulses?
(The application going to drive a stepper motor forward/backward so I need the number of pulses)
/Pelle

I think you probably mean the 6036e, right? I've got 2 basic ideas for you:
1. Always generate continuous pulses and always count on using your software to decide when to stop. This is *probably* not the solution you want, but it would make life simpler if you can live with it. The reason is that continuous pulse trains only require 1 counter so you can just count those pulses with the 2nd counter. Finite pulsetrains use up both counters. I suspect you need the finite pulsetrain though to define a nominal exact distance, but in case your software decides you must stop prematurely, you'd like to know where you are.
2. Configure an AI task or an AO task that uses your counter output as its sampling clock. Then you can query the AI/AO task for a property like "Total Samples Acquired" or "...Generated" to get your step count. You would do the query with a DAQmx property node -- either a Read or Write property node if I recall correctly (not presently near LV to check). Note also that you should start your AI or AO task before starting the Counter task, and if you stop the counter task, do your query before stopping the AI / AO.
-Kevin P.

Finite pulse train with variable pulse widths

Greetings LabVIEW developers,
Does anyone have code that can show me how to use E-series counters to generate a finite pulse train where the individual pulse widths vary? I need to generate a series of 20 pulses with the high time for each pulse randomly varying between 50 and 1000 microseconds. The low time for each pulse needs to be constant (around 50 microseconds).
Thanks,
Ryan Wright

Ryan,
Sorry, but this isn't possible with the counter/timers. I've been wanting this capability myself for about 6 years now.
Personally, I think it's an unfortunate "hole" in product capability. The other major data acq hw allows you to capture and later replicate a signal of interest. You can capture an analog waveform with AI and later play it back with AO. You can capture a digital pattern and later play it back with timed DIO. You can capture buffered semi-periods with a counter -- but you can't play play them back later. So for your app, you'll need to generate the variable freq using timed DIO. The new M-series boards ought to work for this, or a dedicated high-speed digital board.
There's another product that I think is even better for timed DIO though and it's put out by one of NI's "Alliance partners" -- Viewpoint systems. Here's an example of why I like it. Let's say you need to generate 20 pulses within 60 seconds. The times of the pulses need to be precise to within 1 usec, and they have no common divisors. The NI method will require you to use an update rate of 1 MHz and you'll create a buffer of 60 MB to represent the digital pattern at every usec. The Viewpoint method needs a buffer of 40 entries. Each entry is a combination of a timestamp and a pattern to generate at that timestamp. That pattern will just stay there until the next defined timestamp. So all you do is define the digital pattern at the instants when one or more bits will change. It works analogously for digital input - if you capture with 1 usec resolution for 1 minute but there are only 20 pulses (40 digital transitions), you only capture the 40 relevant timestamps & patterns instead of a full 60 MB.
If interested, look for the PCI-DIO64 at Viewpoint's website.
-Kevin P.

Finite pulse train Output

Hi,
I am using a 6602 board and would like to generate a finite pulse train. I have used the example code from Labview (Finite Pulse Train NT-IO) and cannot see both outputs.
I mean I can see the enveloppe on counter +1 (gating counter +0) but cannot see the finite pulse train on Counter +0.
Thanks
W.

Hi
Could you just post you LabVIEW code please
Thanks
Nick

Finite Pulse Train TIO-Timing Specs

Howdy everyone,
Got a question regarding the pulse specs of finite pulse generation with a 6602 (TIO chip).
I'm using a slightly modified version of the Finite Pulse Train (NI_TIO).vi found in the examples directory to produce finite pulses.
The slight modifications are to allow for some hardware triggering. I am using counters 2 and 3 to produce a finite pulse train.
My external electronics provides the trigger to the gating counter.
I want all of my timing specs relative to this external pulse.
Let's say I want a delay of 10 seconds until my first output pulse is produced by the output counter; I want pulses to come every 1 sec; Pulses are 0.5 sec wide.
I know from looking into the VI's that the TOTAL delay--ie the time from my external trigger until the time the output counter outputs a 0.5 sec pulse--is equal to the "initial delay (in secs) in the finite pulse specs cluster in the VI plus the interpulse interval minus the pulse width.
Thus, If I enter a value of 10 seconds for initial delay, I actually expect the first pulse to be output at time = 10 +1 - 0.5 sec = 10.5 sec. This is one-half second later than desired, but it is easy to correct.
Now for my real question:
I'm usually looking at pulses coming about 20 msec after the trigger arrives. The pulse interval is 5msec and the pulses are 0.5 msec wide.
Even when I program my counters to get the timing I want with this correction, ie. implement the formula Desired Delay = "Initial Delay" - (pulse interval - pulse width), I still see my pulse arriving late by 1msec. 1 msec is enough that I care to get it right. I don't understand the source of this delay. Does anyone have any idea what could be happening?
It seems totally independent of any parameters I enter for pulse interval, intial delay, pulse width.
Not sure if it matter, but I'm generating this finite pulse train inside of a much larger VI that is busy collecting and displaying data from a 6071E.
Any thoughts/help would be greatly appreciated!

I'm using Traditional DAQ (not DAQmx), so I think points 3 and 4 are not strictly true for my VI.
(I'm am very hesitant at this moment to think about switching over to DAQmx : I"m at the end of my graduate career and don't have the time to overhaul my program at the moment; and my VI works perfectly for my needs..except the 1msec delay. I'll suggest future lab peoples move to mx...)
As I understand, for traditional DAQ:
1. Start the counter -- I believe it will force the output into its idle state (low by default).
2. Trigger edge occurs
3. Output remains in idle state for "initial delay."
4. Output transitions to armed state and remains low for "low time" which is computed/specified by the "frequency" and "duty cycle" specs. So the total delay is the "initial delay" + "low time"
5. Ouput transitions to high state for a time, also determined/computed by the frequency and duty cycle specs.
6.Thereafter, the times will be based on your regular pulse specs, such as low time / high time.
OK, I didn't want to drag the VI into it, but it seems there is no other way; and I really want to know why my timing is not quite as I would expect.
The VI I posted has 3 outter sequence frames. The action, as far as we're concerned in this post, is in outter frame number 3; inner frame number 3, case True, subVI Finite Pulse Train (NI-TIO)-jev4.vi. This VI is "slightly" modified from the example that came packaged with LV "Finite Pulse Train (NI-TIO).vi" The modifcations I made were 1. removed the while loop that checked the status of the counters, because I needed this subVI to return before the pulse train had actually finished executing. 2. Added start trig capability to the gating counter's gate. (Maybe this is the source of the 1msec error?).
There is a variable "stim delay (msec)" that specifies when the first high pulse should be output from the 6602. (device 2 for me.)
To complicate things further, " stim delay" is actually relative to another variable in Neurochip-legacy.vi called "record delay." Record delay specifies the delay between the the arrival of the trigger pulse and start of data acquisition on NI6071E. (had to do this because of the way things are set up in the lab). This trigger pulse is shared with the 6602--it is hardwired in a breakout box to also be routed to my 6602 card. Thus, if the trigger arrives at time = 0, record delay = 20 msec, and stim delay = 40 msec, I would like to see my first output pulse of the train (on the 6602) come at time = 60 msec.
For the time being I have set the "initial delay" = record delay + stim delay - (pulse interval - Ta), where pulse interval is just 1/"frequency" parameter for finite pulse generation, and Ta is the desired width of the output pulse which in turn specifies "duty cycle" parameter. For the moment, I've also hardcoded in a 1msec correction--which was the whole reason for the original post.
Maybe in all this arithmetic and wiring I've made a goof somewhere...if so, maybe a fresh pair of eyes would help.
Ok, so if you are brave enough to check out the code, it is attached.
If you find that you are getting the same result as me, I would love to know it.
If you are getting different result than me, I'd love to know it.
If you see where I went wrong, I'd really love to know where.
Thanks very much
jon
Attachments:
Neurochip-Legacy.vi.zip ‏637 KB

Loss of Synchronization for Finite Pulse Train generation

I have successfully generated a finite pulse train on my 6608. My program is based off an example I got from NI Zone (Square_Wave_Trigger.zip).
Unfortunately, the Finite Pulse Train loses synchronization every once in a while, and I'm not sure why. Is there anyway to prevent the loss of synchronization???
When I say loss of synchronization, here is what I mean exactly. I'm generating 4 pulses, but every once in a while, when I reprogram my equipment, I lose those 4 pulses. They seem to go out of phase or something.
I have included my code as well (Sync.txt), which is slightly different from the example code. In my code, the finite pulse train is generated by the "Sequence Gating Pulse"
and the "USIP Firing Sequence" lines of code, which are clearly marked.
Any help would be greatly appreciated. =)
Attachments:
Sync.txt ‏14 KB
TIOgenSquareWaveStartTrig.C ‏6 KB

I lose the pulse train until I reset my counters. The pulse train shifts out of phase with the main pulse. It's easier to see in the pictures below.
Attachments:
Good_Pulses.jpg ‏203 KB
Shifted_Pulses.jpg ‏220 KB

Finite pulse train generation?

i am trying to generate a very specific pulse with my tio-6602 in labwindows. after a 20us delay, i want the board to generate 20 pulses, with a width of 1 us and an interval of 5us. ideally, this would be retriggerable at 100 Hz. any suggestions on what would be the best way to approach this problem?

Paco,
You can use a gated pulse train, which is similar to finite pulse train generation. With finite pulse train generation, you have one pulse for the gate of a counter set to generate a pulse train. The pulse train will only be output based on the gate, so if one pulse appears, you have a finite pulse train. Now, if you make the gate be a pulse train itself, then you can continuously output bursts of pulses. For instance, you can set it up such that the pulses are output when the gate is high. When the gate is low, the counter pulses would pause and when the gate resumes to the high states, your pulses would continue. I've attached a code excerpt for using NI-DAQ function calls to generate a finite pulse train that is in our database. I will see abo
ut getting it put onto the http://www.ni.com/support pages. You can also find more information about the function calls used by referencing the NI-DAQ Help file installed with the NI-DAQ driver software and with the NI-DAQ User Manual, which is available at the web pages.
Regards,
Geneva L.
Applications Engineering
National Instruments
http://www.ni.com/ask
Attachments:
finitepulsetrain.txt ‏2 KB

How to generate a bipolar pulse train in LabView using USB DAQ 6211?

Hi,
I am setting up a system to generate either a single square pulse or a train of square pulses using LabView, with controls to adjust the frequency, amplitude, number of pulses etc. I have had a lot of help from NI tech support setting up the actual VI itself which seems to be working fine, and outputting the pulses via a USB DAQ 6211 using a square waveform generator and the AO1 channel on the DAQ.
The problem that I now have is that I need to pulses generated in a train to be bipolar (as they are connected to electrodes so need to be bipolar o avoid salt build up on the electrodes from the voltage going in one direction only, at least that is how I understand it!).
How can I set up my LabView VI to generate a bipolar pulse train instead of always being positive voltage? I am new to this area and so am trying to learn but there is so much to learn!
Thanks,
spamjam

Hi Shalini,
Apologies for taking a while to get back to you, I hope I can explain what it is that we need to create with the pulses. I understand what you mean about the existing pulses having a positive and negative on the graph - but we need the pulses to start from a resting voltage and the first pulse to be positive, then back to zero, then the second pulse to be negative then back to zero etc. This is to do with reversing the direction of the current between two electrodes to prevent build up of salts on one electrod from the current always passing in the same direction.
I have attached a .Tif file to this post to try to illustrate what I mean - the top picture shows how the pulses are currently generated, then bottom on is what we would like to produce if this is possible?
Thanks for your help,
Spamjam
Attachments:
Slide1.jpg ‏38 KB

How do I generate two finite pulse trains using counters on PXI-6251

Similar Messages

Maybe you are looking for