Finite Pulse Train TIO-Timing Specs

Howdy everyone,
Got a question regarding the pulse specs of finite pulse generation with a 6602 (TIO chip).
I'm using a slightly modified version of the Finite Pulse Train (NI_TIO).vi found in the examples directory to produce finite pulses.
The slight modifications are to allow for some hardware triggering. I am using counters 2 and 3 to produce a finite pulse train.
My external electronics provides the trigger to the gating counter.
I want all of my timing specs relative to this external pulse.
Let's say I want a delay of 10 seconds until my first output pulse is produced by the output counter; I want pulses to come every 1 sec; Pulses are 0.5 sec wide.
I know from looking into the VI's that the TOTAL delay--ie the time from my external trigger until the time the output counter outputs a 0.5 sec pulse--is equal to the "initial delay (in secs) in the finite pulse specs cluster in the VI plus the interpulse interval minus the pulse width.
Thus, If I enter a value of 10 seconds for initial delay, I actually expect the first pulse to be output at time = 10 +1 - 0.5 sec = 10.5 sec. This is one-half second later than desired, but it is easy to correct.
Now for my real question:
I'm usually looking at pulses coming about 20 msec after the trigger arrives. The pulse interval is 5msec and the pulses are 0.5 msec wide.
Even when I program my counters to get the timing I want with this correction, ie. implement the formula Desired Delay = "Initial Delay" - (pulse interval - pulse width), I still see my pulse arriving late by 1msec. 1 msec is enough that I care to get it right. I don't understand the source of this delay. Does anyone have any idea what could be happening?
It seems totally independent of any parameters I enter for pulse interval, intial delay, pulse width.
Not sure if it matter, but I'm generating this finite pulse train inside of a much larger VI that is busy collecting and displaying data from a 6071E.
Any thoughts/help would be greatly appreciated!

I'm using Traditional DAQ (not DAQmx), so I think points 3 and 4 are not strictly true for my VI.
(I'm am very hesitant at this moment to think about switching over to DAQmx : I"m at the end of my graduate career and don't have the time to overhaul my program at the moment; and my VI works perfectly for my needs..except the 1msec delay. I'll suggest future lab peoples move to mx...)
As I understand, for traditional DAQ:
1. Start the counter -- I believe it will force the output into its idle state (low by default).
2. Trigger edge occurs
3. Output remains in idle state for "initial delay."
4. Output transitions to armed state and remains low for "low time" which is computed/specified by the "frequency" and "duty cycle" specs. So the total delay is the "initial delay" + "low time"
5. Ouput transitions to high state for a time, also determined/computed by the frequency and duty cycle specs.
6.Thereafter, the times will be based on your regular pulse specs, such as low time / high time.
OK, I didn't want to drag the VI into it, but it seems there is no other way; and I really want to know why my timing is not quite as I would expect.
The VI I posted has 3 outter sequence frames. The action, as far as we're concerned in this post, is in outter frame number 3; inner frame number 3, case True, subVI Finite Pulse Train (NI-TIO)-jev4.vi. This VI is "slightly" modified from the example that came packaged with LV "Finite Pulse Train (NI-TIO).vi" The modifcations I made were 1. removed the while loop that checked the status of the counters, because I needed this subVI to return before the pulse train had actually finished executing. 2. Added start trig capability to the gating counter's gate. (Maybe this is the source of the 1msec error?).
There is a variable "stim delay (msec)" that specifies when the first high pulse should be output from the 6602. (device 2 for me.)
To complicate things further, " stim delay" is actually relative to another variable in Neurochip-legacy.vi called "record delay." Record delay specifies the delay between the the arrival of the trigger pulse and start of data acquisition on NI6071E. (had to do this because of the way things are set up in the lab). This trigger pulse is shared with the 6602--it is hardwired in a breakout box to also be routed to my 6602 card. Thus, if the trigger arrives at time = 0, record delay = 20 msec, and stim delay = 40 msec, I would like to see my first output pulse of the train (on the 6602) come at time = 60 msec.
For the time being I have set the "initial delay" = record delay + stim delay - (pulse interval - Ta), where pulse interval is just 1/"frequency" parameter for finite pulse generation, and Ta is the desired width of the output pulse which in turn specifies "duty cycle" parameter. For the moment, I've also hardcoded in a 1msec correction--which was the whole reason for the original post.
Maybe in all this arithmetic and wiring I've made a goof somewhere...if so, maybe a fresh pair of eyes would help.
Ok, so if you are brave enough to check out the code, it is attached.
If you find that you are getting the same result as me, I would love to know it.
If you are getting different result than me, I'd love to know it.
If you see where I went wrong, I'd really love to know where.
Thanks very much
jon
Attachments:
Neurochip-Legacy.vi.zip ‏637 KB

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Delayed retriggerable finite pulse train

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CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

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How do I output a finite pulse train through multiple counters?

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Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:36 AM
Message Edited by Knights Who Say NI on 02-02-2009 10:38 AM
-John Sullivan
Analog Engineer
Attachments:
4xcount.jpg ‏67 KB

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Tiano,
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Ryan,
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Finite pulse train with different frequency

Hello,
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Attachments:
pulse train finite mod.vi ‏38 KB

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CORRECTION TO PREVIOUS POSTING THERE WAS AN ERROR IN HOW I DESCRIBED THE PROBLEM:
I have a problem using a retriggerable finite pulse train as in the NI example Retriggerable_Finite_Pulse_Train. I use ACTOUT to gate the first re-triggerable pulse control and the second pulse control generates the continuous pulse train which is gated by the first retriggerable pulse control. The ACTOUT signal is generated by an AI control which senses a crank trigger (Hall Sensor). The re-triggerable pulse train is used to modulate a fuel injector in sync with ignition timing and RPM. If the period of the ACTOUT signal changes due to a change in RPM, the pulse train is recalculated. It works OK with one hitch. Even at constant RPM, after about 15 re-triggerer pulse trains the final pulse of the train does not complete. This leaves the signal high in-between successive re-triggerer pulse trains. This incorrect high signal between re-triggerer pulse trains means that the fuel injector is incorrectly left on in-between pulse trains. This incorrect high signal goes on for about 10 pulse train events and then returns to normal. This pattern repeats. I use the ActualPeriod of the second control's continuous pulse train to ensure the pulse train ends correctly within window of the first re-triggerable pulse. This work but with time this pulse train seem to shift slightly. Is there another way to create a different type of re-triggerable pulse train that overcomes this problem?

Finite pulse train generation?

i am trying to generate a very specific pulse with my tio-6602 in labwindows. after a 20us delay, i want the board to generate 20 pulses, with a width of 1 us and an interval of 5us. ideally, this would be retriggerable at 100 Hz. any suggestions on what would be the best way to approach this problem?

Paco,
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ut getting it put onto the http://www.ni.com/support pages. You can also find more information about the function calls used by referencing the NI-DAQ Help file installed with the NI-DAQ driver software and with the NI-DAQ User Manual, which is available at the web pages.
Regards,
Geneva L.
Applications Engineering
National Instruments
http://www.ni.com/ask
Attachments:
finitepulsetrain.txt ‏2 KB

Finite pulse train generation... how to count number of pulses?

hi guys,
this has probably been solved a hundred times but i just couldnt find it!!
i have a pulse train generation happening on my ni usb-6211... using FREQ OUT, using a divisor on this, and routing it to PFI4.
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dan
Attachments:
pulse train generation.vi ‏25 KB

Hi,
No problem at all, we are here to help. What I’m going to do first is to point you to a bunch of examples for that might give you a better insight of the capabilities of the card in terms of finite pulse generation. What you should be looking at is called retriggerable pulse generation and here are some examples to look at: Retriggerable Finite Pause Trigger Digital Pulse Train Generation, Creating a Delayed, Retriggerable and Finite Pulse Generator, DAQmx - Retriggerable Pulse Train Generation - LabVIEW - CVI - ANSI C - VB.NET - C#.NET and Retriggerable Finite Pulse Train with Changing Pulse Specs.
Let me know it helps
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How do I generate two finite pulse trains using counters on PXI-6251

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Inside the disabled box is what I'd like to run on both counters. I stripped things down to creating the task, starting, and stopping. I then started to add things to see what my problem was. The timing VI seems to be what causes me issues but I don't know why.
My end objective is two identical pulse trains with one delayed by 5us, which I figured would be easy to do in the initial delay. I tried both in a single task and as separate tasks with no avail.
Attachments:
2_counter_outputs.vi ‏32 KB

Hi SirMutt,
Creating a finite pulse train requires
two counters. What’s really happening is that one counter is creating a
continuous pulse train while the other counter applies a finite pulse to “window”
the pulse.
What you want to do is correlated DIO. I’ve
done a search on our website for “correlated DIO” and have come up with a few
resources. Hopefully that will help you get started.
Digital Output and Pulse Generation
Performing Correlated Digital IO with an M Series Device in LabVIEW
M Series Hardware-Time DIO with Counter Clock Generation
Mark E.
Precision DC Product Support Engineer
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Need to unreserve a counter in a finite pulse train generation

Hi. Let´s introduce my application first: I´m trying to generate a N-pulse train with the M series PCI-6221, in order to achieve a high frequency clock for an SSI transducer. That´s why i can´t use a software generation (because of the high frequency) and i have to use a finite pulse train. Besides, I would need to use another counter for a variable and finite count (but not simultaneously). The problem is that, as i think i have understood, this finite pulse train involves the two counters working together, so I can´t programm another task with that resources.
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Hello,
My knowledges tell me that you need two counter to generate a finite pulse train.
The first counter generates a pulsed of desired width and the second counter generates the pulse train which is gated by the pulse of the first counter (Counter 0=Pulse Generation, Counter 1=Pulse train generation).
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Maybe you can try with a continuous pulse train generation and with this method you have another counter to do a finite count.
Regards
DiegoM.

How do you create a finite pulse train using a FP-CTR-502?

I have recently replaced my FP-PG-522 module with a FP-CTR-502 module, to achieve higher output frequencies (FP-PG-522 max output freq is 5kHz, wheras the FP-CTR-502 max output freq is 16 kHz).
I need to be able to generate a finite pulse train. Has anybody created a finite pulse train using a FP-CTR-502 module before? I have started to look into it, but my ideas so far have been complicated (compared to doing it in a PG module).
Any tips on this would be much appreciated.
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au
Solved!
Go to Solution.

I can answer this question myself!
The answer is in the *OLD* version (July 2000) of the operator's manual for the FP-CTR-502. For some reason, this has been removed from the latest version (June 2003).
See page 11 of this link for more information:
http://www.ni.com/pdf/manuals/322660a.pdf
Christopher Farmer
Certified LabVIEW Architect
Certified TestStand Developer
http://wiredinsoftware.com.au

Inverting and outputing a finite pulse train

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Attachments:
4xcount.jpg ‏67 KB

You could write out the same signals to the 4 more lines and invert the logic on those lines using a channel property node»digital output»invert lines.
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National Instruments Condition Monitoring

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