FPGA: are typedef coercion dots bad for efficiency?

Howdy--
Using LV 2011 FPGA, I always get coercion dots when reading or writing to/from FIFO or Memory items typed with a typedef.ctl.  Do these indicate some extra use of resources in the compiled code, or are they harmless?
Thanks a bunch all, and have a great day.
--Brad
Solved!
Go to Solution.

bcro wrote:
Awesome.  For a minute there I was afraid I'd have to abandon typedefs..a scary prospect when you're as scatter-brained as I am.
Thanks a bunch Taper for the quick reply.  Be Well.
Too answer this question yoursefl you could use
Tools >>> Profile "Show Buffer Allocations...
To bring up a toll that will show where the buffers are being created.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction

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