Fpga: dynamic mode vs type def for FPGA ref

What are the differences for dynamic mode and type def for FPGA referenece?  When should I use which?  Is there a scenerio when I should use neither?
Kudos and Accepted as Solution are welcome!

So, you can still create a Type Def of a Dynamic Interface Refnum... That sounds confusing I know. Basically, my design flow is generally as follows:
Develop initial FPGA code.
Create a Control or Type Def with the FPGA Interface control configured for my FPGA VI.
Develop my host, and use the Type Def in all of my subVIs.
If I need to edit my FPGA code, now I only have to update the control in the typedef to propagate my interface changes to all of my subVIs
Basically, every project I do has a FPGA Reference typedef for use in my host VI.
Attached, you can find a (incomplete) sample project of mine that does this.
Cheers!
TJ G
Attachments:
Sample Project.zip ‏233 KB

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