FPGA courant

Bonjour à tous!
Voilà j'ai un petit problème, j'ai en ma possession un PXI 7851R que je contrôle bien évidemment sous LabView, et dont les sorties analogiques sont connectées à un contrôleur de polarisation. Seulement il semblerai que le contrôleur nécessite une alimentation en courant continue de 100mA pour fonctionner correctement. Le hic c'est que le courant délivré par le FPGA est de 4mA. donc je pense qu'il me faudra un amplificateur de courant qui le multiplirai par 25 ... quels sont les moyens d'y arriver ? je ne suis malheureusement pas electronicien donc je ne sais pas trop quoi faire...
j'attends vos idées et votre aide avec impatience.
Merci d'avance!
Yanis

Je rejoint l'avis de Rodéric : une alime externe avec en plus un amlpificateur opérationel de puissance (un AO ou AOP qui peut délivrer pas mal de courant) en gros vous monter votre AO en motage type "suiveur" alimenté par une alimentation externe capable de délivrer un peu de puissance. Avec le montage montage "suiveur" l'AO délivrera la même tension sauf qu'il pourra fournir plus de puissance si vous le choissez bien. Par exemple un L165V alimenté avec du +/- 10 V, par contre il pourra pas aller au delà de 1000KHz je crois.
Bien cordialement
Dcharala, Ingénieur en instrumentation, pratiquant de LabVIEW 2010 sur Windows XP.

Similar Messages

Calculer période signal avec labview FPGA

Bonjour,
je cherche à calculer la période/la fréquence d'un signal d'un couplemètre avec sortie fréquentielle < 5-10>kHz, en utilisant le labview FPGA.

Bonjour Addoula,
Merci d'avoir posté sur le forum National instruments.
Pour réaliser une mesure de fréquence ou de période, il est courant d'utiliser un ou plusieurs compteurs.
Au lien ci-dessous, vous trouvez un document expliquant les techniques pour effectuer ce genre de mesure:
http://www.ni.com/white-paper/7111/fr/
Pour réaliser un compteur avec labview FPGA, le document suivant vous montre un petit exemple:
http://www.ni.com/white-paper/2993/fr/
Bonne journée.
Cordialement
Aurélien Corbin
National Instruments France
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Report generation for FPGA VI

Hello..
I want to include the number of resources used by FPGA (LUTs, slices, blockrams etc) in my report generation.
After compilation is completed, a window showing these resources will occur. But, how can I add this compilation report in my report generation...
Please let me know..
Thanks
Prashanth
Solved!
Go to Solution.

Hi
I made a small code which helps you achieve this functionality.
Hope it helps!
In this code: I read from "toplevel_gen_xst.log" file generated for the project; search for the string "Device utilization summary" and extract the part of interest Now you add this extract to your report compiled using report generation toolkit.
regards,
Ravi.
Attachments:
image.jpg ‏60 KB
FPGA Utilization.vi ‏10 KB

Help with SERIAL FPGA

I have a PWM project runing in FPGA target. And my execution file is working very well but just with Ethernet. I would like to do a project that a person who will execute this file can choose witch communication to use. Other words I just want to know how to implement serial communication on my project.
Of portuguese: Eu tenho um projeto em FPGA de um pwm simples. Criei o meu arquivo executavel e esta tudo funcionando bem porem em comunicacao Ethernet. Gostaria agora de criar o mesmo projeto, porem em comunicao serial.
Please someone give me a help!

Good morning,
Here are some links with examples to assist in its implementation. Any questions please contact us.
RS-232 Interface Reference Example for LabVIEW FPGA
https://decibel.ni.com/content/docs/DOC-7946
RS-232/RS-422/RS-485 on a FPGA Target
http://zone.ni.com/devzone/cda/tut/p/id/9595
Can You Implement RS-232, RS-422, or RS-485 with NI FPGA Hardware?
http://digital.ni.com/public.nsf/allkb/7ADB475DF68DAB518625713A0052799A?OpenDocument
Sincerely,
Mauro Vera
Applications Engineer
National Instruments

NI9203 - Need to know how to set up the FPGA code for multiple NI9203 modules and how to calibrate the data

Hi. I'm using the NI9203 module to detect pressure, temerature and flow rate of water in a cooling system. I have 17 different inputs coming in therefore i'm using 3 NI9203 modules. I've used the example provided with labview as a base for designing my code. The example can be found here : Program Files\National Instruments\LabVIEW 8.0\examples\CompactRIO\Module Specific\NI 9203.
I've had no problems when testing this code out for a single NI9203 module but when i add code for 3 modules the code will not compile as my resources are over mapped. Is there a simpler way to program the FPGA code.
That said how do you go about calibrating the data that's received from the module. Preferably i'd like to write a vi to do the calibrating. Just need help on how to go about writing this vi

Hi havok,
Firstly, I would use constants to configure the modules, it'll save some resources on the FPGA. I'm not typically changing the settings on the fly, so using constants whenever possible helps. I would also take a look at the following KnowledgeBase article on other changes you can make to the FPGA VI to compile the code:
http://digital.ni.com/public.nsf/allkb/311C18E2D635FA338625714700664816?OpenDocument
The best changes you can make are to use fewer arrays and front panel elements. This can be done by using a DMA FIFO or constants on the block diagram.
Now actually calibrating the data will require you to do it on the host side. There is an example VI called Binary to Nominal that changes the raw data to something more useful for datalogging, display, etc. It can be found in some of the example VIs, or in the following link:
http://digital.ni.com/public.nsf/allkb/E86D8D460C4C092F8625752F00050A61?OpenDocument

How to pass the sequence number of current loop in a for loop in FPGA vi to the host

PCI-7830R
LV 8.2
What I was trying to do is to use multiple DIO to generate pulse at different sequence. Mode one is to automatically sweep from DIO1 to DIO20; mode 2 is several DIOs generate pulse simoutaneously. So I use a case structure to make the selection, in the mean time, I set up two for loop in each case so that I can use multiple pulse generations. For example, in scanning mode, if I set 2 exposures, it sweeps from 1 to 20 then do it again.
Then I need to get the loop sequence number, i of each scenario. So I put an indicator within the first loop, and create a local variable of it and put in the second one. Running the FPGA vi alone, I can see the indicator change in each case from 0 to N-1, N being the for loop time.But in the host vi, I tried to add this indicator as an element in the read/write invoke method, in the debugging mode, I could only see it directly jump to N-1 without all the changes I saw in FPGA vi.
Is it possible to get this number passed correctly from FPGA vi to the host vi? Thanks

Thanks for the reply Jared.
Excuse me if it looks incorrect, but I'm new to FPGA programming, so I would have to look into the FIFO you referred to. I used local variables because for one thing I have several different cases containing for loop in each of them, and I only want one indicator for the "i". If I put the indicator out of any for loop, it's only gonna show the last number which is N-1. For the other thing, it seems like property nodes are not allowed in FPGA vi. And by doing this, I can see the i number changing from 0 to N-1 in each case, well, in FPGA vi's front panel. But while I ran the host vi with everything, the indicator in host vi's front panel only showed the last number N-1. It may be the reason you said, it happened too fast before the indicator in host vi can catch it.
What I want to realize is to group the data I collect in host vi, for example, when I choose multiple exposure in each mode, and the FPGA runs 1 through 20 then do it again, I want the data stored in two groups using the loop sequence number as the seperator in file name. So it goes like 1-1, 2-1.......20-1; then 1-2, 2-2,.....20-2.

MyRIO FPGA FFT Express VI timing analysis for multiple input mode - trying to perform fft's on a 3-axis accelerometer

Hi Everyone!
Project Background:
I've been working with the myRIO FPGA in an attempt to generate an application capable of sampling a tri-axis accelerometer and performing an fft on each axis. I've successfully developed an application for a single axis, but attempting to duplicate the code to sample the second and third axes in parallel results in an estimated 150% resource utilization for the tiny FPGA's LUT's. Additionally, I'm looking to avoid sequentially processing each accelerometer input using triggers and a single fft block because that reduces my fft update frequency significantly (e.g. I can't calculate another fft for input 1 until I calculate an fft for inputs 2 and 3).
After reading up on the fft vi, I'm thinking that I can use the M-interval input indexes / Continuous output indexes Input/Output Index Pattern mode. My thought is that I can edit the vi to remove any math that "recombines" these three vectors into a single fft, resulting in 3 separate fft's. I'm also hoping that this process requires less time than using the sequential method described above.
The Questions:
1. Has anyone done an fft on three inputs using the myRIO at sampling rates > 20kHz and fft sizes of 1024 or larger? If so, I may just be lacking some proper resource management.
2. Does anyone know where to find timing information on the M-interval input indexes / Continuous output indexes Input/Output Index Pattern mode? The manual only provides timing diagrams for singel channel / single input modes. I don't want to waste my time modifying the vi if it will still take 3x as long (assuming modifying the vi is even a possibility).
Further Information:
I already have an application written that samples the accelerometers at >20kHz and then performs the fft on the main processor, but now I'm looking to see if it is possible to perform all signal processing on the FPGA side. The processor performs decently enough, but the timing is not as consistent as I would like it to be. Lastly, I am aware that the myRIO itself has a built in accelerometer, but I need to mount the accelerometer in an environment where the myRIO would probably be damaged and definitely cannot fit.
Any thoughts are much appreciated! The excessive FPGA compile times for this thing make the old guess and check method less appealing.
-Chris

Hi Chris,
Thanks for posting and the detailed background on the project! To answer some of your questions:
1. The FFT Express VI does use a significant amount of space. The FPGA on the myRIO is somewhat limited space-wise. Your best option may to implement the FFT for 1 channel on the FPGA and the other two on the RT side.
2. I converted the FFT Express VI to a subVI and I am not sure if you can trim too much code from it. The subVI is also very complex so re-working it would be a significant amount of work. I could not find much documentation on M-interval input indexes / Continuous output indexes Input/Output Index Pattern mode timing.
I hope that this helps!
Thanks,
Frank
Application Engineer
National Instruments

How to download an FPGA vi along with a real time application

Hello
I am targeting cRIO 9012, cRIO 9102. I downloaded the FPGA vi on flash memory and then built a real time application and set it as startup. But there was no signals on the modules IOs which are handled by FPGA vi.
Also the shared variables of that application when running as standalone aren't accessible. Please provide me the steps that should be followed to access the shared variables of a standalone real time system. Please help me resolve these problems.
Best Regards
Mani

Hi Mani,
What modules do you have? What kinds of signals are you measuring?
Have you deployed your shared variable library on your host PC?
Regards,
Jeremy_B
Applications Engineer
National Instruments

Using Host and FPGA.vi in Teststand

Does anyone know how to use the Host and FPGA vi's in Teststand?? A National App Engr told me I have to call the Project that the vi is in to get all the functionality of the FPGA. How do you call a Project in Teststand??
Thanks

Ensure you are using the TestStand version 2010 or above. Create a new instance of a sequence and add a LabVIEW action step to it. Go to Module panel and browse for a LabVIEW project as displayed below.

160 counters in FPGA. Use arrays or 160 loops?

I need to program a 7811R FPGA module to give me 160, 16 bit counters. Originally I made 4 loops (one for each connector) and put the counts from each loop in a 40 element array - mostly to make it easier to program. I'm wondering if that's a bad idea. Would it be better to use an individual loop for each counter? Or maybe use one array per 8 bit port (20, eight element arrays)? I don't have my board yet so I haven't been able to test it.
George

Hello George!
I am terribly sorry I misread your previous question. You want to check for pulses on 160 lines and then keep track of the number of pulses in a 160 element array. I believe this is the only efficent way todo this but I am concerned whether their will be enough real estate on the FPGA to handle this 160 element array. Additionally, its going to take some time to read and process 160 lines at the same time. Therefore you may want to break this up into 20 loops of 8 lines so that you are not waiting for one loop todo all the processing. This would also give you 8 arrays of 20 elements. Sorry it took me so long to get on the same page with this issue. I hope this helps and please continue to write if you have more questions.
Allan S.
National Instruments

Communication problem between FPGA VI and Host-PC VI

Dear,
I am trying to set up communication between an FPGA an the host-PC using FPGA FIFO's.
The communication still has some problems and I don't know what would cause them.
Labview gives me the following reason "The transfer did not complete within the timeout period or within the specified number of retries."
What is wrong with my labview program? How can i solve this?
The Project can be found in attachment.
Best regards,
Jasper Beurms
Solved!
Go to Solution.
Attachments:
CEC20_02.zip ‏150 KB

Hello Jasper,
Are you fully familiar with how DMA FIFOs work on a cRIO?
Some general questions:
- Is there a specific reason that you need to use DMA FIFOs?
You seem to only require a 10 msec acquisition rate?
- Wouldn't it be easier to just use the Scan Engine in the case you don't need to go below 10 msec?
The Scan Engine should allow you to do acquisitions at this rate without even having to implement FPGA code yourself.
Another benefit is that the Shared Variables created/published by the Scan Engine are also by default visible over the network/
If want to use DMA FIFOs, then I would suggest you take a look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/
I would advise that you read out the DMA FIFOs on a VI that is running on the RT Controller (RT VI) and then send those values from the RT VI over the network to your Windows VI.
You could use for example Shared variables to sent values from the RT VI to the Windows Host VI.
Another solution might be to use network streams or more custom TCP/IP communication.
If these concepts are new to you, then please have look at the Compact RIO Developer's Guide: http://www.ni.com/compactriodevguide/
This Guide should explain you all the basics you need to know.
If something is unclear or requires further explanation, then please let me know.
Kind Regards,
Thierry C - Applications Engineering Specialist Northern European Region - National Instruments
CLD, CTA
If someone helped you, let them know. Mark as solved and/or give a kudo.

Problem with combination of LabVIEW classes (dynamic dispatch), statechart module and FPGA module

SITUATION:
- I am developing a plug-in-based software with plug-ins based on LabVIEW classes which are instanced at run-time. The actual plug-in classes are derived from generic plug-in classes that define the interfaces to the instancing VI and may provide basic functionality. This means that many of the classes' methods are dynamic dispatch and methods of child classes may even call the parent method.
- Top-level plug-ins (those directly accessed by the main VI) each have a run method that drives a plug-in-specific statechart.
- The statechart of the data acquisition plug-in class (DAQ class) calls a method of the DAQ class that reads in data from a NI FPGA card and passes it on to another component via a queue.
PROBLEM:
- At higher sampling rates, an FPGA-to-host FIFO overflow occurs after some time. When I "burden" the system just by moving a Firefox browser window over the screen, the overflow is immediately triggered. I did not have this kind of problem in an older software, where I was also reading from an FPGA FIFO, but did not make use of LabVIEW classes or statecharts.
TRIED SOLUTIONS (WITHOUT SUCCESS):
- I put the statechart into a timed loop (instead of a simple while loop) which I assigned specifically to an own core (I have a quad-core processor), while I left all the other loops of my application (there are many of them) in simple while loops. The FIFO overflow still does occur, however.
QUESTION:
- Does anybody have a hint how I could tackle this problem? What could be the cause: the dynamic dispatch methods, the DAQ statechart or just the fact that I have a large number of loops? However, I can hardly change the fact that I have dynamic dispatch methods because that's the very core of my architecture...
Any hints are greatly appreciated!
Message Edited by dlanger on 06-25-2009 04:18 AM
Message Edited by dlanger on 06-25-2009 04:19 AM
Solved!
Go to Solution.

I now changed the execution priority of all the VIs involved in reading from the FPGA FIFO to "time critical priority (highest)". This seems to improve the situation very much: so far I did not get a FIFO overflow anymore, even when I move around windows on the screen. I hope it stays like this...

Why does opening and closing FPGA references increase Windows XP handles by 3?

Hello.
We run a test system here that uses TestStand to communicate
to a number of Labview VI modules which in turn communicates to a
PXI-7833R FPGA. Everything has been working fine except after a long time running Labview would get an out of memory error. I discovered
after a particular VI was run 100,000 times, the number of handles in Windows XP Task
Manager grew to about 370,000. The number of threads and processes remains stable and normal. Closing Labview removes all the excessive handles.
I tried an experiment to create a standalone VI (ie: no TestStand) which simply opens the FPGA VI reference then closes the reference. This is repeated 4 times in the same VI. The number of handles in Windows XP Task
Manager increased by 12 each time the VI was run. No errors. This indicates closing the FPGA reference might not be working.
Why does this happen? Is there a way to avoid it? The version of Labview is 8.5.1.
Appreciate any help here. Thanks.
-Dave

could be related to this known issue--
FPGA FIFO reset behavior—When you use an FPGA target
emulator, FPGA FIFOs reset when the VI is stopped and then started
again. When you use an FPGA target with Interactive Front Panel
Communication, FPGA FIFOs do not reset when the FPGA VI is stopped and
then started again. To reset the FIFO, right-click the FPGA target in
the Project Explorer window and select Download
from the shortcut menu. When you control an FPGA VI using Programmatic
FPGA Interface Communication, use the Close FPGA VI Reference function
with the Close and Reset shortcut menu option selected or the Invoke Method with the Reset method selected to reset FPGA FIFOs
see Knowledgebase
Also remeber to load the FPGA Read/Write VI's dynamically from testStand and dump them after. Thechange to the data type causes the vi to need to recompile so it can't stay in memory if you need different types of data.
Message Edited by Jeff Bohrer on 10-27-2009 02:21 PM
Jeff

Multiple issues with PCI-5640R FPGA: DAC and Strange Execution at Host

We are working on a communications systems project using the PCI-5640R
IF-RIO transceiver and the FPGA module. At the FPGA, a sequence of bits are
being modulated through multiplication with the sine wave generator. The
next step is to take the modulated sinusoidal signal and send it through the
DAC. Throughout this project, we have been using the Analog Input and Output
example project from Getting Started with the 5640-R IF... as a template
to build this project. There are, however, several issues/questions we
have. Attached are the HOST and FPGA vis that we are working with.
1. The host only runs every other time. At the host (BPSK_TX(HOST).VI, the execution gets
halted for an infinite period of time at one of the FIFOs until 'stop' is
hit. But then at the subsequent execution, the host completes execution
of the program. In other words, the host is only receiving data from the
FPGA every second time it is run. Why is this happening? Are we missing
something at the host or FPGA VI?
2. How exactly do we send our own digitized signal through
the DAC? As seen in one of the FPGA VIs, we have tried modfiying the
output section of the FPGA VI in the Analog Input and Output project in which
the FPGA reads from the FIFO. In our case, we are modulating the signal
in a separate section, writing it to a target-scoped FIFO and then reading from
that FIFO and processing the data as in the example. This modified FPGA
vi is "BPSK_TX(FPGA).VI)
Unfotunately, we are not observing anything at an oscilloscope
connected to the transceiver. Even when we try to pass in a
"custom" signal at the HOST we have no luck observing anything
coherent. As seen in the bare_sine_wave_test (FPGA).vi, we have
attempted a relatively simple way of sending a signal through the DAC, yet
still no luck. I am guessing that this is related to issue #1.
On a related note, when
receiving the signal and running it through the ADC, what steps are
necessary? Can one assume that it is
similar to the FPGA.VI in the analog input and output example?
3. How do for loops and while loops synchronize with timed loops
and frames in the FPGA? In the FPGA we are using a for loop to
modulate the signal because the sine wave generator cannot be contained within
a timed loop on the FPGA. This will be important to us because at the
receiver we will need to know the symbol rate in order to recover the signal.
I would sincerely appreciate any feedback or help that can be provided
on this,
Attachments:
BPSK_TX(FPGA).vi ‏152 KB
BPSK_TX(HOST).vi ‏257 KB
bare_sine_wave_test (HOST).vi ‏135 KB

It may be that the FPGA Refernce has not been binded. The issue was that the VIs need to be bound to the ni5640R FPGA VI Reference.ctl control. This is an option on the popup menu when clicking on the Open FPGA VI Reference VI. In some cases, it may already be selected in the popup menu. In this case, unselect the Bind to Typedef option. For good measure, I usually selected the FPGA VI to use with the host VI, and then I reset the Bind to Typedef option. In most cases this should fix the ni5640R FPGA VI Reference.ctl control mismatches throughout the VI. In some cases, I have to Save All, close the host VI and all subVIs. Then reopen the host VI. This has always working in all cases for me.
Jerry

What happens to FPGA code when a module it expects is missing?

Hi Folks,
I want to know what happens if you have FPGA code that expects a module to be present running on a system where the module is missing.
We have a RT control system that runs on a cRIO 9014 with a 9111 backplane. There are only two modules in the slots and one of these is the Prosoft Profibus module. The biggest chunk of the FPGA code is taken up with configuring and sending and receiving using this module. Specifically the communications with the module are done by the Read (Memory) and Write (Memory) structures.
We are developing code to use the Ethernet/IP libraries instead of Profibus in some cases. This means the communications moves from the FPGA to the RT. We are considering have the ability to switch be an option.
My concern is that if the FPGA has code in that references the Profibus module, then it might behave badly if the module is not present.
And so my question is if FPGA code tries to reference a module that is not present, what happens? Is it just an error? Will there be no error? What?
Thanks!

I am not familiar with profibus, but why not just remove the module and run it and see what happens? I'm guessing you will get an error, althougth which error I am not sure.
CLA, LabVIEW Versions 2010-2013

FPGA courant

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