Calculer période signal avec labview FPGA
Bonjour,
je cherche à calculer la période/la fréquence d'un signal d'un couplemètre avec sortie fréquentielle < 5-10>kHz, en utilisant le labview FPGA.
Bonjour Addoula,
Merci d'avoir posté sur le forum National instruments.
Pour réaliser une mesure de fréquence ou de période, il est courant d'utiliser un ou plusieurs compteurs.
Au lien ci-dessous, vous trouvez un document expliquant les techniques pour effectuer ce genre de mesure:
http://www.ni.com/white-paper/7111/fr/
Pour réaliser un compteur avec labview FPGA, le document suivant vous montre un petit exemple:
http://www.ni.com/white-paper/2993/fr/
Bonne journée.
Cordialement
Aurélien Corbin
National Instruments France
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How to take a derivative of a signal in Labview Fpga
How to make derivative of a position signal acquiring using AI module of cRIO to get the velocity signal.
I got one example in forum and i m attaching that, bt i need to implement this in FPGA.
Note : The position is varying at 30Hz to 80Hz Freq.
Attachments:
derivative.jpg 48 KB
derivative.jpg 48 KBI forgot to mention that one problem with numerical differentiation is that if you have a noisy signal, the noise is amplified!
You can try implementing a moving average or median filter in the FPGA code. There are a number of previous threads and Community posts on these, ranging from simple implementations to more complex ones. Try using the search function at the top of the page to look for them.
Of course, it's easier to acquire the raw data, send it to the RT host and do your processing there, depending on resources.
Regarding the sampling time, you have hopefully set this via the tick delay you set in the FPGA acquisition loop.
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How to generate a chirp(linear FM) signal using dds theory in LabVIEW FPGA.
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FPGA DDS SineGen IP.vi 42 KByou need to increment the "accumulator increment" during the duration of the chirp. the "accumulator increment" controls the frequency of the DDS cycle. by increasing it's value, you are increasing the frequency. the math for increment values follows the same math as determining the frequency to increment value.
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Labview FPGA 2012 - Clock Signal
I'm trying to access the FPGA clock signal in Labview 2012. I have a NI PCIe-7852R card, with which I'm using the 40MHz onboard clock signal. I'd like to use that signal to clock some logic in my design, but there seems to be no easy way to access it - or, at least, the "clock signal" component has its own data type which only connects to a timed loop (the logic in question is in the form of a VHDL black box, which requires multiple clock rates; therefore since the IP integration node only allows one signal to be tied to the clock I need others as well, which will be fractions of the onboard clock). Any advice?
I use a SCTL running @ 20MHz to generate a 10MHz clock.
All you need is a SCTL with an Invertor on the IO Line and shift registers to hold the last state of the IO.
Each time the SCTL runs the IO is inverted and output. You should be a 50% Duty Cycle Clock.
Visualize the Solution
CLA
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Bonjour,
Je tiens d’abord à préciser que je suis un novice en ce qui concerne Labview.
Je développe une expérience pour la mesure des moments d’inertie. Pour cela, j’ai besoin de mesurer l’accélération angulaire d’une roue. J’ai acheté une « photogate head » qui délivre un signal carré de 5V lorsque la roue tourne ( style encodeur). La période de chaque cycle de ce signal me permettra de calculer la vitesse de rotation de la roue à un instant donné. Le nombre de cycle est limité (i.e. le signa n’est pas continu). A partir du graph v=f(t), les étudiants pourront calculer l’accélération angulaire.
J’ai acheté une carte d’acquisition NI-6008. Avec Labview, j’arrive à acquérir un signal carré analogique provenant d’un générateur ( avec le VI « lire » DAQmx) et à l’écrire dans un fichier.
Avec le VI « mesure d’impulsion », j’arrive à mesurer la période et la durée d’impulsion, mais uniquement pour le premier cycle. Ce que je veux c’est mesurer la période pour des cycles allant de n= 1 à N et écrire un fichier (temps, période ou vitesse) afin de calculer l’accélération. J’ai essaye d’utiliser une boucle « For » sur l’entrée « numéro d’impulsion » du VI (mesure impulsion) mais sans succès.
Que dois-je faire ?
Est-ce que j’utilise une méthode correcte ou existe-t-il une solution plus simple ?
Merci pour votre aideBonjour Lou60,
Grâce à Rodéric, il n'y a plus d'erreur au niveau de votre VI. Toutefois, comme il l'avait signalé auparavant, vous avez un problème de structure. En effet, pour réaliser la mesure N fois, vous devez inclure dans votre boucle for la fonction daqmx read, ceci afin d'acquérir de nouvelles données Je vous envoie un exemple qui doit convenir à votre application.
Cordialement
Nb: vous pouvez directement glisser l'image que je vous envoie dans le diagramme de LabVIEW
Mathieu B
National Instruments France
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Pièces jointes :
mesure signal carre.png 49 KB -
hello,
I an new in LabVIEW FPGA programing so I would appreciate any help. I am using sb-rio 9636 card and optocoupler for speed messaurment of DC motor. I have conected everyting right and the sensor is giving me date. But messauring the speed the oscilations of sensor data are huge. I am not changing the speed and motor continiousliy is rotating in the same speed but data are not the same. For example im 12 V that is the max speed motor schould rotate in 6500 rpm/min but in one second it is showing 6500 and in the other 5500 rpm/min. think that there is not problem in the code but that the messaurment are not reliable. I will put my code. I need to know is there anz other way to do encoder readings.
Thank youI don't see anything in your loop that guarantees the timing of your sampling of the digital encoder pulses. It appears you expect that loop to run at 1MHz based on the uS unit label on your time of flight indicator.
Because you are using front panel indicators for some of your calculation variables, I can't see all the numbers going into your calculations.
How much variance do you see in the time of flight measurement on your front panel? You must remember that you are making measurements in whole integers of uS. How much change in the RPM calculation do you see if the uS measurement drifts by 1 uS?
If the impact of 1uS change in pulse to pulse measurement has a big impact on your calculation, then you will need to adjust your algorithm to get a more precise measure of the time of flight.
Some ideas:
The faster your sampling loop runs, the more likely you will sample the signal right after the pulse transistion. Consider using a Single-Cycle Timed Loop to sample at speeds in the 40MHz (25ns period) range. This will give you more precision. One risk I can't rule out in your existing code is that you may be sampling slow enough that in some cases you miss a pulse completely. If you want to ensure that you do not miss any pulse edged, then you must ensure that the loop is sampling at least 2x the frequency of your pulse train, assuming the pulses have a clean 50% duty cycle. If that duty cycle is not 50%, then the maximum sampling period must be shorter than the shortest pulse you expect.
Rather than measuring the time difference from pulse to pulse, measure the time of 10 pulses, or 1000 pulses, or some other larger number. This averages a larger number of pulses so that the difference of 1us resolution has less impact on the calculated measurement.
-
High Speed Clock Signal Generation Using FPGA Ouput
Hi,
This a screen shot of a LabVIEW FPGA program. Here I am trying to generate 5MHz Clock signal at Connector 0 DIO12. But I get around 2MHz when I measure the signal using an oscilloscope. Would some tell me what’s wrong ?
LabVIEW 2011
FPGA Target : PXI 7841
I set DIO 12 to Nerver Arbitrate in the property setting.
Solved!
Go to Solution.I'm not certain but maybe some of the delay is happening because you are changing the mode of the pin. According to the specs on the card it is capable of having a Maximum Clock Rate of 40MHz under the DIO section. So if you are purely doing digital reads, or digital writes you should be able to update/read 40,000,000 times a second. If you perform a read, which can take up to 1/40M of a second, then invert which takes some time but practically none, then another write which can take up to 1/40M of a second, your loop rate should still be faster than the 10MHz you showed. That's why I suspect there is time involved in changing over the pin from a read mode to a write.
If you try to do something similar with the analog you'll notice the maximum update rate is only 1MHz. So while your logic and code can run at 40MHz you can only update the analog value at 1MHz. Because of this in the past I have had two loops. One running a at the maximum clock rate doing the logic calculations, and then sending the result to another loop that updates the output at the maximum rate which in the case of an analog out is only 1MHz.
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How to import Verilog codes into LabVIEW FPGA?
I tried to import Verilog code by instantiation followed by the instruction in http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3,
but still I can see some errors while compiling the VI file.
Simple test Verilog file is as follows:
==============================
module andtwobits (xx, yy, zz);
input xx, yy;
output reg zz;
always @(xx,yy) begin
zz <= xx & yy;
end
endmodule
==============================
and after following up the above link, we created the instantiation file as
==============================================
library ieee;
use ieee.std_logic_1164.all;
entity mainVHDL is
port(
xxin: in std_logic;
yyin: in std_logic;
zzout: out std_logic
end mainVHDL;
architecture mainVHDL1 of mainVHDL is
COMPONENT andtwobits PORT (
zz : out std_logic;
xx : in std_logic;
yy : in std_logic);
END COMPONENT;
begin
alu : andtwobits port map(
zz => zzout,
xx => xxin,
yy => yyin);
end mainVHDL1;
==============================================
Sometimes, we observe the following error when we put the indicator on the output port,
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq_ms*" TNM =
TNM_ChinchIrq_IpIrq_ms;> [Puma20Top.ucf(890)]: INST
"*ChinchLvFpgaIrq*bIpIrq_ms*" does not match any design objects.
ERROR:ConstraintSystem:58 - Constraint <INST "*ChinchLvFpgaIrq*bIpIrq*" TNM =
TNM_ChinchIrq_IpIrq;> [Puma20Top.ucf(891)]: INST "*ChinchLvFpgaIrq*bIpIrq*"
does not match any design objects.
and interestingly, if we remove the indicator from the output port, it sucessfully compiles on the LabVIEW FPGA.
Could you take a look at and please help me to import Verilog to LabVIEW FPGA?
I've followed the basic steps of instantiation on the above link, but still it won't work.
Please find the attachment for the all files.
- andtwobits.v : original Verilog file
- andtwobits.ngc: NGC file
- andtwobits.vhd: VHD file after post-translate simulation model
- mainVHDL.vhd: instantiation main file
Since there is no example file for Verilog (there is VHDL file, but not for Verilog), it is a bit hard to do the simple execution on LabVIEW FPGA even for the examples.
Thank you very much for your support, and I'm looking forward to seeing your any help/reply as soon as possible.
Bests,
Solved!
Go to Solution.
Attachments:
attach.zip 57 KBHi,
I am facing problem in creating successfully importing VHDL wrapper file for a Verilog module,into LabVIEW FPGA using CLIP Node method. Please note that:
I am working on platform SbRIO-9606.
Labiew version used is 2011 with Xilinx 12.4 compiler tools
NI RIO 4.0 is installed
Xilinx ISE version installed in PC is also 12.4 webpack ( Though I used before Xilinx 10.1 in PC for generating .ngc file for verilog code FOR SbRIO 9642 platform, but problem remains same for both versions)
Query1. Which versions of Xilinx ISE (to be installed in PC for generating .ngc file) are compatible with Labview 2011.1(with Xilinx 12.4 Compiler tools)? Can any version be used up to 12.4?
Initially I took a basic and gate verilog example to import into LabVIEW FPGA i.e. simple_and.v and its corresponding VHDL file is SimpleAnd_Wrapper.vhd
///////////////// Verilog code of “simple_and.v”//////////////////////
module simple_and(in1, in2, out1);
input in1,in2;
output reg out1;
always@( in1 or in2)
begin
out1 <= in1 & in2;
end
endmodule
/////////////////VHDL Wrapper file code of “SimpleAnd_Wrapper.vhd” //////////////////////
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY SimpleAnd_Wrapper IS
port (
in1 : in std_logic;
in2 : in std_logic;
out1 : out std_logic
END SimpleAnd_Wrapper;
ARCHITECTURE RTL of SimpleAnd_Wrapper IS
component simple_and
port(
in1 : in std_logic;
in2 : in std_logic;
out1 : out std_logic
end component;
BEGIN
simple_and_instant: simple_and
port map(
in1 => in1,
in2 => in2,
out1 => out1
END RTL;
Documents/tutorials followed for generating VHDL Wrapper file for Verilog core are:
NI tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. Link is http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3
In this case, I did not get any vhdl file after “post-translate simulation model step” in netlist project using simple_and.ngc file previously generated through XST. Instead I got was simple_and_translate.v.
Query2. Do I hv to name tht “v” file into “simple_and.vhd”?? Anyways it did not work both ways i.e. naming it as “simple_and with a “v” or “vhd” extension. In end I copied that “simple_and.v” post translate model file, “simple_and.ngc”, and VHDL Wrapper file “SimpleAnd_Wrapper.vhd” in the respective labview project directory.
Query3. The post-translate model file can also be generated by implementing verilog simple_and.v file, so why have to generate it by making a separate netlist project using “simple_and.ngc” file? Is there any difference between these two files simple_and_translate.v generated through separate approaches as I mentioned?
2. NI tutorial “Using Verilog Modules in a Component-Level IP Design”. Link is https://decibel.ni.com/content/docs/DOC-8218.
In this case, I generated only “simple_and.ngc” file by synthesizing “simple_and.v “file using Xilinx ISE 12.4 tool. Copied that “simple_and.ngc” and “SimpleAnd_Wrapper.vhd” file in the same directory.
Query4. What is the difference between this method and the above one?
2. I followed tutorial “Importing External IP into LABVIEW FPGA” for rest steps of creating a CLIP, declaring it and passing data between CLIP and FPGA VI. Link is http://www.ni.com/white-paper/7444/en. This VI executes perfectly on FPGA for the example”simple_and.vhd” file being provided in this tutorial.
Compilation Errors Warnings received after compiling my SimpleAnd_Wrapper.vhd file
Elaborating entity <SimpleAnd_Wrapper> (architecture <RTL>) from library <work>.
WARNING:HDLCompiler:89"\NIFPGA\jobs\WcD1f16_fqu2nOv\SimpleAnd_Wrapper.vhd" Line 35: <simple_and> remains a black-box since it has no binding entity.
2. WARNING:NgdBuild:604 - logical block 'window/theCLIPs/Component_ dash_Level _IP_ CLIP0/simple_and_instant' with type 'simple_and' could not be resolved. A pin name misspelling can cause this, a missing edif or ngc file, case mismatch between the block name and the edif or ngc file name, or the misspelling of a type name. Symbol 'simple_and' is not supported in target 'spartan6'.
3. ERROR:MapLib:979 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainInd icator/cQ_0_rstpot" (output signal=window/theVI/ Component_dash_Level _IP_bksl_out1_ ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot) has input signal "window/internal_Component_dash_Level_IP_out1" which will be trimmed. SeeSection 5 of the Map Report File for details about why the input signal willbecome undriven.
Query5. Where lays that “section5” of map report? It maybe a ridiculous question, but sorry I really can’t find it; maybe it lays in xilnx log file!
4. ERROR:MapLib:978 - LUT6 symbol "window/theVI/Component_dash_Level_IP_bksl_ out1_ind_2/PlainIndicator.PlainIndicator/cQ_0_rstpot" (output signal= window / theVI/Component_dash_Level_IP_bksl_out1_ind_2/PlainIndicator.PlainIndicator/ cQ_0_rstpot) has an equation that uses input pin I5, which no longer has a connected signal. Please ensure that all the pins used in the equation for this LUT have signals that are not trimmed (see Section 5 of the Map Report File for details on which signals were trimmed). Error found in mapping process, exiting.Errors found during the mapping phase. Please see map report file for more details. Output files will not be written.
Seeing these errors I have reached the following conclusions.
There is some problem in making that VHDL Wrapper file, LabVIEW does not recognize the Verilog component instantiated in it and treat it as unresolved black box.
Query6. Is there any step I maybe missing while making this VHDL wrapper file; in my opinion I have tried every possibility in docs/help available in NI forums?
2. Query7. Maybe it is a pure Xilinx issue i.e. some sort of library conflict as verilog module is not binding to top VHDL module as can be seen from warning HDLCompiler89. If this is the case then how to resolve that library conflict? Some hint regarding this expected issue has been given in point 7 of tutorial “How do I Integrate Verilog HDL with LabView FPGA module”. http://digital.ni.com/public.nsf/allkb/7269557B205B1E1A86257640000910D3. But nothing has been said much about resolving that issue.
3. Because of this unidentified black box, the whole design could not be mapped and hence could not be compiled.
P.S.
I have attached labview project zip folder containing simple_translate.v, simple_and_verilog.vi file,SimpleAnd_Wrapper.xml, Xilinx log file after compilation alongwith other files. Kindly analyze and help me out in resolving this basic issue.
Please note that I have made all settings regarding:
Unchecked add I/O buffers option in XST of Xilinx ISE 12.4 project
Have set “Pack I/O Registers into IOBs” to NO in XST properties of project.
Synchronization registers are also set to zero by default of all CLIP I/O terminals.
Please I need speedy help.Thanking in you in anticipation.
Attachments:
XilinxLog.txt 256 KB
labview project files.zip 51 KB -
LabVIEW FPGA PMW modulation for L298n H-bridge
Hello to everyone,
I am new in LabVIEW FPGA programing and I have a couple questions, so I would be grateful if you could answer me. For my final work I have to control the speed and direction of DC motor using sb-RIO 9636 and H-bridge L298n. In attachments you can find scheme of the H- bridge and my program. I have conected In1(pin 5 of L298n) to digital pin 1 of the card, In2(pin 7 of L298n) to digital pin 2 of the card and changing the state of the pin I change the direction of the motor(I know that the one In should be Low and the other High so the motor can rotate in one or the other direction). PWM(Enable pin of the L298n pin 6) I have conected to DIO3.
PWM signal I cretaed is shown in picture.
My questions are:
1.Will loop timer I used, provide that period of signal is lenght I specify in the control(for example if I put 20 000 will the period be 20000 s)?
2. Can I vary the duty cycle changing the control Waiting (DIO3 is HIGH for a couple of us, then it sets LOW, and then all that repeats )?
3. Earlier I thaugt that PWM signal I should send in both IN1 and IN2, and that the Enable pin is used to stop or start the motor. I tried that and the motor was rotating different speed, and I could stop or star the motor with enable pin, sending it HIGH OR LOW, but I could not change the direction of the motor. So my other option was to conect the pins as I explained at the begining. My question is: Should I PWM conect to the enable pin, and will thah work?
Thank youI found a couple of resources that deal with PWM on the FPGA and motor control - they might be helpful to reference as you look for answers to your questions.
Developing a PWM Interface using LabVIEW FPGA
http://www.ni.com/white-paper/3254/en/
CompactRIO Motor Control Basics Tutorial
http://www.ni.com/pdf/labview/us/compactrio_motor_control_basics.pdf
PWM Output With LabVIEW FPGA
http://www.ni.com/example/26499/en/ -
LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
Hello NI forums,
Question:
See the attached picture from a modified version of the LabVIEW DRAM FIFO example. It probably explains my question more effectively than the paragraphs below.
What is the difference to the LabVIEW / Xilinx compiliers, if any, between placing two independent branches of code in the same SCTL, versus placing them in individual SCTLs (in the same clock domain)?
Misc. comments:
I have briefly experimented with this concept using the included LabVIEW DRAM FIFO example (example finder >> Hardware Input and Output >> FlexRIO >> External Memory >> Simple External Memory FIFO.lvproj).
I compiled the default example (the read and write interfaces are in separate 40MHz SCTLs) five separate times. Then I put the read and write interfaces in the same 40MHz SCTL and compiled another five times. The result (when both read and write interfaces were in the same SCTL) was a reduction in resource usage (according to the compilation summary).
However, due to my lack of knowledge I'm hesitant to conclude that placing everything in one SCTL is always the best option. For example, I do not know what is created 'behind the scenes' with each SCTL. Perhaps putting independent branches of code in separate SCTLs makes it possible to route clock, reset, implicit enable, etc. signals more effectively.
Background information:
My task involves acquiring 2 channels of analog data using the NI 5772 and PXIe-7966. Data acquisition takes place in a 200MHz SCTL, and downstream processing is performed in a 100MHz SCTL.
During a vast majority of the 100MHz SCTL processing stages of the FPGA VI, the 2 channels of data do not interact with eachother. So it would be easy for me to place them in separate 100MHz loops if doing so would somehow help the design (timing, resource usage, etc.).
Thanks!
Attachments:
question.png 76 KBIntaris
Trusted Enthusiast
Posts: 3,264
Re: LabVIEW FPGA: Multiple SCTL versus one SCTL (same clock domain)
10-28-2014 12:11 PM
Just out of interest, what is the resource usage differential between the two versions?
In response to the above comment,
This is a little embarrassing, but it seems like the resource usage is similar than I initially thought for this particular example. I think the previous compilations that I based my assumption on coincidentally used more resources in the 2-SCTL loop case. I just compiled each version two additional times (see below).
Here's the version with everything in one loop:
Device Utilization
Total Slices: 17.6% (2587 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4855 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 16.9% (2493 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4858 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Here's the version with the read and write in separate loops:
Device Utilization
Total Slices: 16.4% (2407 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.2% (4852 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244)
Device Utilization
Total Slices: 19.4% (2859 out of 14720)
Slice Registers: 9.5% (5583 out of 58880)
Slice LUTs: 8.3% (4859 out of 58880)
DSP48s: 0.0% (0 out of 640)
Block RAMs: 2.5% (6 out of 244) -
Acquiring data in LabVIEW FPGA
Hello,
I am working on LabVIEW FPGA where I have to acquire data from a source and take its average. One way to do that is to keep adding every new signal to the sum f the older ones and then average.
However, I wish to store all the incoming values into a file and save it. But when I tried doing so, it gives an error saying "array size cannot be changed". With this constraint, I am unable to write the data into an array.
Please suggest.
Thank you.
Dheeraj Bharadwaj
IIT-Madras
Solved!
Go to Solution.You need to acquire data, pass it to the RT, then log there. You cannot use build array on the FPGA because FPGA will not allow for dynamically allocating memory like this. You must preallocate the array then use replace array subset. A better way is to use DMA FIFOs. Have a look at the FPGA examples in LabVIEW for streaming data. Then, on the RT, you can just add in your file logging functions.
CLA, LabVIEW Versions 2010-2013 -
RS 422 @ 8Mbit/s is it possible with Labview FPGA??
Hi,
I've to read and write data over an RS422 link at a rate of 8Mbit/s.
Do you think it's possible to implement RS422 @8Mbit/s with labview FPGA?
I know that I will have to make electrical adaptation to use RS422 signals with FPGA card.
Can the FPGA IP available on this website do this?
Thanks a lot
JulesjayChristophe wrote "Yes it's possible to implement this into FPGA, if you adapt the electrical signal."
Are you sure ?
Depending on if that spec is baud vs bit rate and the over-sampling implemented in most serial read logic, the FPGA may not be able to cycle fast enough.
Ben
Ben Rayner
I am currently active on.. MainStream Preppers
Rayner's Ridge is under construction -
Générer un signal avec signal express (erreur 200077)
Salut à tous,
J'ai acquis une carte NI PCI 6010 et je la pilote via Labview Signal Express.
Ce que je veux c'est émettre un signal (admettons sinusoïdal) sur une des sorties analogiques de la carte. Je créé donc ce signal avec l'étape "Créer un signal analogique", puis j'ajoute une étape "DAQmx - Générer" et là il y a une "Erreur de l'Assistant DAQ" qui arrive! Cela correspond à l'erreur 200077 qui annonce qu'il y a un problème avec le type de cadencement d'échantillonnage.
J'ai alors ouvert un exemple préinstallé dans Labview Signal Express qui génère un signal sinusoïdal et le problème persiste.
Merci de m'aider le plus vite possible.Bonjour.
L'erreur que vous rencontrez indique que vous essayez d'utiliser une propriété dans votre génération qui n'est pas compatible ou disponible sur votre carte.
J'ai refait les mêmes étapes que vous et je n'ai pas d'erreur.
Quelle est l'amplitude du signal que vous voulez générer et quelle fréquence d'échantillonnage choisissez-vous?
Cordialement. -
Enlever la composante continue d'un signal dans la FPGA
Bonjours,
Je cherche à enelever la composante continue d'un signal dans ma FPGA, pour cela j'ai essayé d'utiliser un filtre butterworth passe haut d'ordre deux avec fc= 20Hz, celui-ci m'enlève bien la composante continue mais il me laisse un offset à la sortie, certe petit mais un offset quand même et vu qu'après cela j'ai besoin d'intégrer mon signal cette offset est très embêtant. J'ai essayé avec d'autre filtre créer avec le IP core generator mais le problème reste le même.
Avez vous une idée de comment procéder pour enlver la composante continue d'un signal avant de l'intégrer avec Normalized Discret integrator.vi?
Cordialement
Sébastien KuenlinBonjour Skuenlin,
Avez-vous essayé d'augmenter la fréquence de coupure de votre filtre de manière à atténuer plus fortement les basses fréquence?
Quelle est la fréquence minimum du signal que vous souhaitez récupérer?
Si cette fréquence est proche du DC avez-vous pensé à utiliser un autre type de filtre "tchebycheff" ou autre, ou simplement augmenter l'ordre de votre filtre?
Cordialement,
Rémi D.
National Instruments France
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Bonjour à tous!
ça fait quelques jours maintenant que j'essay de me mettre à LabView FPGA et je galère trop ! je n'arrive à trouver ni tutoriaux ni exercices qui pourraient me permettre de comprendre le fonctionnement et la programation d'une borne fpga... j'ai essayé d'y aller au feeling mais bon... c'est pas gagné !
dejà, quelle est le lien entre LabView real-time et Labview FPGA ?
suis je obligé d'utiliser LabView real-time pour commander ma borne FPGA ?
ou puis je trouver des manuels d'initiation ?? (l'anglais ne me pose pas de probleme)
je sais que ces questions parraissent ETREMEMENT basique, mais croyez moi, j'ai pas mal cherché et n'ai rien trouvé ...
Merci d'avance,
YanisBonjour,
LabVIEW FPGA et LabVIEW RT sont deux modules différents qui pris a part n'ont rien à voir l'un avec l'autre...Si vous me parlez des deux c'est surement que votre matériel exige l'utilisation des deux modules pour fonctionner.
Vous devez certainement utiliser un CompactRIO qui fonctionne avec un processeur temps réel et une puce FPGA.
Je vous conseil dans un premier temps de lire ce tutoriel rapide : http://zone.ni.com/devzone/cda/tut/p/id/3358
Et ensuite de vous tourner vers ces guides : http://www.ni.com/compactriodevguide/f/
Cordialement,
Da Helmut
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