FPGA digital output time

Does anybody knows the typical time that a FPGA card, like PXI 7831, take to generate a TTL signal on one of its digital lines?
To be much clear, imagine you read a digital line on your PXI 7831 as fast as possible (40 MHz...?) and then generate a TTL high signal when you see a rising edge on digital input...What you be the delay between the two signals?

The delay between reading an edge on the input line and updating an ouput line will depend on the exact requirements of your application and the implementation of the code based on that. There are two main ways to implement this type of application.
You can continuously read the input line and then in your LabVIEW code check for a change of state and if one is detected, update the output line. The delay between reading the input and updating the output will be 2 or 3 clock cycles of the FPGA (50-75 ns at 40 MHz). However since this code would be running in a loop, the loop overhead is added to the possible delay as the change on the input line may occur at any time. So the maximum delay may be around 6 to 8 clock cycles.
The second method to implement t
his code is to use the Wait for Edge function in LabVIEW FPGA. This function will wait for an edge on a digital input line and continue when an edge is detected. The delay will be 2 to 3 clock cycles, however the application will not be cycling through the loop if no edge is detected.
Depending on the complexities of your diagram you may be able to compile your code for an 80 MHz FPGA clock rate in which case the delays would be cut in half.
Christian L
NI Consulting Services
Christian Loew, CLA
Principal Systems Engineer, National Instruments
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