Fpga digitizing speed

Hello All,
thanks in advance for this great forum!!!
my system is a chassis pxi-1042 with a RT controller pxi-8106 and an FPGA 7831-R.
I'm new with LV FPGA and I was trying to create a symple analog input program (I put them in attachments).
the problem is that with signals in the range of 10-20 Hz everything seems to work fine.
If I put in input to the fpga a signal with higher frequency (also only at 50 Hz) the system has strange behaviours, it is like the fpga has a digitizing speed that is not enough.
I set the fpga clock to 40 MHz.
did I miss some settings?
thanks a lot for the support!!
ciao
Mario
Attachments:
Analog Input (FPGA).vi ‏70 KB
Project-Screenshot.jpg ‏83 KB
Analog Input (Host).vi ‏214 KB

Mario,
You may want to pass more than one data point at a time with your DMA fifo. Also, the write to file function you are using is not the best choice for high speed streaming.
Take a look at this example that Basset Hound put together.
SteveA
CLD
FPGA/RT/PDA/TP/DSC
Attachments:
RIO DMA with Polling, Scheduling, Interrupts.zip ‏1166 KB

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I have simplified my program to something very basic to replicate the problem.
The digital output D0 switches on and off everytime the realtime loop cycles through.
If I run just the FPGA seperate and turn on the digital output control D0 it stays on solid. (until I turn it off again)
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FPGA Digital Channel Read

I am using the PCI-7831R, and the signal is connected to Channel 2.
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You define your signals as either a digital line (serial read/write) or a digital port (parallel read/write). This can be seen if you add FPGA I/O to your target. Here's some screenshots of both single and port signals:
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Attachments:
fpga io3.png ‏3 KB
fpga io.png ‏11 KB
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FPGA digital output time

Does anybody knows the typical time that a FPGA card, like PXI 7831, take to generate a TTL signal on one of its digital lines?
To be much clear, imagine you read a digital line on your PXI 7831 as fast as possible (40 MHz...?) and then generate a TTL high signal when you see a rising edge on digital input...What you be the delay between the two signals?

The delay between reading an edge on the input line and updating an ouput line will depend on the exact requirements of your application and the implementation of the code based on that. There are two main ways to implement this type of application.
You can continuously read the input line and then in your LabVIEW code check for a change of state and if one is detected, update the output line. The delay between reading the input and updating the output will be 2 or 3 clock cycles of the FPGA (50-75 ns at 40 MHz). However since this code would be running in a loop, the loop overhead is added to the possible delay as the change on the input line may occur at any time. So the maximum delay may be around 6 to 8 clock cycles.
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his code is to use the Wait for Edge function in LabVIEW FPGA. This function will wait for an edge on a digital input line and continue when an edge is detected. The delay will be 2 to 3 clock cycles, however the application will not be cycling through the loop if no edge is detected.
Depending on the complexities of your diagram you may be able to compile your code for an 80 MHz FPGA clock rate in which case the delays would be cut in half.
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FPGA Digital Signal Output Problem

Hi,
I am having a problem outputting a signal through my PCI-7831 and would appreciate any advice anyone has as I am beginning to crack the wall where I am banging my head into it.
My software is LV7.1 with FPGA module 1.1. I am controlling a VI compiled onto the PCI-7831 with a host VI in windows. I am viewing the outputs I mention on a high end oscilloscope. I'm relatively new to LV and very new to the FPGA module.
The FPGA VI consists of 3 while loops though only 2 loops are not performing as expected. The FPGA while loops in question contain a single sequence structure that has as their first frames an IRQ 0 and 1 respectively .
In the host VI I am waiting for IRQ, writing the value of 2 wait timers, and acknowledging the IRQ in the first frame of a sequence. The FPGA then sets the states of 2 DIO outputs to both high. Then the timers keep both outputs high until the next frame is reached, then 1,0 is written, the second wait expires, and the loop repeats until the while loop conditions in the host VI are met and the sequence in the host VI indexes (this is about 1 second.)
For the second loop, I am going to the next frame in the host VI. This host works the same as the above sequence but only 1 value is being written, 0,1.
In any case, it works but has 2 bugs I can't reason.
The last, and only the last, iteration of the "both high" period is wrong. The 1,1 becomes 1,1, then 0,1 about halfway through the wait, then the 1,0 occurs properly, then the 0,1 period begins properly.
The other bug is that at the beginning of the 1,1; 1,0 sequence the 1,0 is repeated twice.
I am using these signals to control a custom high amplitude bipolar digital signal generator.
I have posted my VI's if anyone would like to see them.
Thanks,
Ben
Message Edited by bugsmashers on 07-21-2005 12:57 PM
Message Edited by bugsmashers on 07-21-2005 12:58 PM
Attachments:
Preset_power_top_WHILE_loops1.vi ‏311 KB
Digital Pulse Amplitude Control Preset Power.vi ‏216 KB
preset_power_data_gen_FPGA.vi ‏684 KB

Hi Ben-
I took a look at your code, and I can explain the first error you are talking about, but I don't think I understand the second error. For the first error, lets start on the last iteration of the first while loop in your host code. It first waits on IRQ 0, then sets the 'high' and 'low' parameters on RT, then acknowledges IRQ 0. At this point on the FPGA side, the top loop (1,1 loop) begins to execute and sets the lines to 1,1. Meanwhile back on the host, your first loop completes and the second loop starts. The first thing the second loop does is wait on IRQ 1. It doesn't have to wait at all because IRQ 1 was set long ago when the FPGA program started, so it clears IRQ 1, and the second FPGA Loop immediately sets the lines to 0,1. The next thing that happens is your top loop in FPGA (1,1 loop) finishes waiting for the time specified in 'high' and moves to the next sequence frame and sets the lines to 1,0, next the second loop finishes its wait ('Wait Zero') starts the loop over again, sends IRQ 1, which is handled by your second host loop, it acknowledges IRQ 1, and then your second FPGA loop sets the lines back to 0,1. Long explanation, but I hope not too confusing. Synchronizing the host and FPGA with everything happening in parallel can get to be a lot to wrap your brain around.
One comment on the code - From your description and looking at the code it looks like the first pulse iterates for a given period of time, then the second. The way you have it written right now the pulse period will not be very deterministic - especially if you are using windows as your host. The reason is that every iteration of the pulse depends on an IRQ interaction, which means you are waiting on your host CPU to do something. Granted, the host should react quickly, but it is not deterministic - if windows is your host, and you start dragging windows around, you'll notice your period become longer than 'high'+'low'. A better architecture might be to send the number of iterates of the 1,1 - 1,0 loop you want to execute down to FPGA, and let FPGA count the iterations and report back when it's done. Then start the second loop, or send all the info down to FPGA and let it control both loops. If setting 'high', 'low', and 'wait zero' need to happen through out, use the read/write control to just update those on the fly from the host rather than making the FPGA halt while they are updated. If determinism on the period length is not important for your code, or you designed it the way you did for other reasons, then ignore everything I just said .
Good luck, sorry I couldn't help on the second problem, if it's still an issue, post back with a little more detail on what '1,0 is repeated twice' means
Dustin

FPGA digital inputs

I'm using an NI 7811R. This might be a stupid question, but do the digital inputs on the 7811R have a specific impedance or current limit?
When I plug my quadrature pulse signal into the 7811R (via connector block) I get a reduction in voltage. Additionally, the quadrature input pulses seem to show up slightly on different digital channels. For example, I can see a blip on channel A when channel B goes to a zero.
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Hi Pewt,
Generally speaking the input impedance can be assumed to be relatively high in relation to the TTL standard, i.e. very little current will be drawn or sunk. It is hard to define this precisely with TTL due to its variation under different conditions which is why I believe a value hasn't been provided on the datasheet.
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MIG 3.92 for Spartan 6 LX9/LX16 DDR2 max speed

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Hi,
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Sbrio 9612 digital input

I have found a really nice example on how to measure frequency on a fpga digital input. However, when I am trying to find the same method I can't find the wait for rising edge method. Where can I find that or what am I missing?
Thanks,
Eric.

I just ran in to the same problem. My code worked fine on a 7853R, but when I ported it over to sbRIO 9632, LabVIEW throws an error and doesn't recognize my wait on falling edge. Basically after reading the forums and scanning the help, it appears that the method is not available for all targets... specifically the 9632 for me. So I'm going to have to create my own logic for the rising edge.
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Attachments:
sbRIO9612 IO Methods.png ‏164 KB
7853R IO Methods.png ‏206 KB
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Why is this .vi slow ?

I use this rather uncomplicated .vi for an one hour continuously monitoring displayed digitized signals thru the GPIB output of my Tektronix DSA 602 ( Digitizing Signal Analyzer, sampling up to 2 Gs/Sec ).
If I tweak the Signal Analyzing Scope at its fastest, its own screen update rate is about 14 mS/screen update ( ~ 70 screens/Sec ).
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Attachments:
Tek_DSA_600_Window_Cont._Display.vi ‏29 KB

I have no experience with the reading of the waveform, but there are a few other thing that could contribute to the slowdown. Maybe you could do a few tests to see what helps (Some suggestions are more cosmetic in nature and probably won't make a big speed difference).
(1) Avoid overlapping controls, they slow down the redrawing of the front panel. Your counter is currently placed on top of the graph!
(2) Change the counter indicator to I32.
(3) Try to limit updating the graph to maybe a few times/second. Do you really need to graph it every iteration? (See attached code image). The human eye cannot see 70 screen updates/second!
(4) If possible, disable autoscaling for x and y.
(5) How often does the x-axis (offset, multiplier) actually change?
Maybe you can set these values using an attribute node only once whenever they change and just feed the plain data array to the waveform graph, avoiding the bundling.
LabVIEW Champion . Do more with less code and in less time .
Attachments:
tek.gif ‏5 KB

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Hello,
For an application, I need to acquire a parallel bus at 25MHz with an 7854R.
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I can create a 100MHz clock and use it in a SCTL to check if a rising edge appears on my clock line and acquire the data line (24 lines of data) but I don't understand what the 40MHz limitation for the DIO means.
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Solved!
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The clock of the FPGA is 40MHz. So that is the maximum rate of the inputs/outputs of the FPGA (Digital I/O). What you could do is use a method node on the clock line to "Wait on a Rising Edge", read the data, and send the data out of a FIFO or DMA. Put that inside of a loop and you should be good to go.
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Hello,
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Message Edited by Andrew_E on 07-17-2009 11:50 AM
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High Speed Clock Signal Generation Using FPGA Ouput

Hi,
This a screen shot of a LabVIEW FPGA program. Here I am trying to generate 5MHz Clock signal at Connector 0 DIO12. But I get around 2MHz when I measure the signal using an oscilloscope. Would some tell me what’s wrong ?
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I'm not certain but maybe some of the delay is happening because you are changing the mode of the pin. According to the specs on the card it is capable of having a Maximum Clock Rate of 40MHz under the DIO section. So if you are purely doing digital reads, or digital writes you should be able to update/read 40,000,000 times a second. If you perform a read, which can take up to 1/40M of a second, then invert which takes some time but practically none, then another write which can take up to 1/40M of a second, your loop rate should still be faster than the 10MHz you showed. That's why I suspect there is time involved in changing over the pin from a read mode to a write.
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Fpga digitizing speed

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