Fpga I/O viewer

Hello everyone,
Is there some kind of tool where you can see which state each IO pin of the FPGA (mine is PXI-7842R) has? If not, can anybody tell me how I can monitor the status of the FPGA IO pins?
I have a large program that changes the output lines at different places (I know, bad programming, but its a test program) so it is hard to keep track in which state all the outputs are. Some kind of tool for this could be very useful.
I'm not sure if just reading the signals with a I/O node in a seperate loop will work because these pins should be set as Digial Out only.
Best regards,
Dries

Hello Dries,
I think this is the tool you're looking for:
https://decibel.ni.com/content/docs/DOC-5560
Kind Regards,
Thierry C - Applications Engineering Specialist Northern European Region - National Instruments
CLD, CTA
If someone helped you, let them know. Mark as solved and/or give a kudo.

Similar Messages

Programmatically calling an FPGA vi to view over the FP vi

Good morning. I have become stumped on this question for a bit so I thought I would post the question here.
Q: what is the best way to programmatically call a VI running on the FPGA to the FP main VI running on a touchscreen computer, where when the FPGA VI is called it goes to the top level of the screen without interrupting the VI output of the main VI?
I have researched using a queued message handler but couldn't get it to function properly. I have also researched dynamically calling a VI and asynchronously calling a VI but am unsure how to implement the correct one for what I are trying to accomplish.
What I am trying to overcome here has to a lot with tab control on the front panel VI as I have discovered that apparently while a tab is open to the top of the FP the other tabs do not I/O any values to the cRIO. This is good and bad for our application. The good part is that it allows a 'locking out' of other processes while the visible tab is on top. But the bad part is that if I open another tab then what I have running on the previous tab stops. I need to be able to incorporate both of these aspects in our program.
This example shows how I am using tabs in our program. (ATTACHMENT 1)
So in the example above, when page 5 is opened the graph indicator starts which is what I need, and when it closes it stops which is correct to.
But the issue is that when page 5 is open it also stops what’s happening on the other four tabs in the same tab pane which is NOT what I need to happen.
What I have done so far to correct this is - removing the page I need to open on top and made it into its own VI.
What this separate VI does is accept input from the FPGA resources including J1939 engine information through an NI9862 card and voltage / analog signals from sensors via an NI9207 card and reads the information on virtual indicators and gauges as seen here. So it makes sense to me to put the VI on the FPGA. (JPEG)
The information on this VI only needs to be seen periodically via the FP by the operator as it is called via a Boolean control (button) on the FP, but it still needs to run on the FPGA when not seen in order to pass information to the RT control for alarm processing. So in that, in the case of an alarm it causes something else to happen to the unit being controlled (ie. Execute an engine shutdown over the J1939 bus)
What this VI cannot do is interrupt the operations that are being executed by the main VI on the FP if called (to do a parameter check) but put the main VI into a ‘locked out’ mode if there is an alarm.
So then the question becomes how to call this VI from the Front Panel VI?
Well, I have tried to make a Queued Message Handler work which it did partially (I was able to open the VI and run it but I couldn’t work out how to close it) and unfortunately I have sub-sequentially erased that bit of programming code. Though I don’t think it would have worked anyway as I was trying to call it as a sub-vi in the main VI that was located on the computer and not on the FPGA target.
Then I tried dynamically calling the VI and found it did the same thing as if the VI were still connected to the tab control by stopping the I/O of the main VI while it was called to the front. I erased that bit of code work too.
So then I started looking at asynchronously calling the VI as I saw that it would allow both VI’s to run at the same time. Here I seem to have found the right answer to my own question, though, I believe that the example program I am looking at has a memory leak or is not closing out the called VI properly because within a few minutes runtime both VI’s slow to a stop. This is not good. I understand what the example code is trying to show but I don’t think it is programmatically correct and I have not been able to fix it. Here is the example code I was looking at. (ZIP FILE)
So while I believe I am on the right path I am not sure how to impliment it with the FPGA.
Solved!
Go to Solution.
Attachments:
Ultimate Tab Control.vi ‏32 KB
ENGINEVI.jpg ‏384 KB
example.zip ‏26 KB

You are correct, that is how the program is built. Each page of the tab has it's own set parameters to interact with the FPGA differently. (ie electromechanical controlling a hydraulic pump so each page has a distinct set of limitations on what the pump control does) this effectively creates a set of 'modes' for different parameter pump control to the same individual pump.
Here is a screen of the main program. The buttons at the bottom determine which mode the pump is in (effectively changes the tab control to a different tab)
So yes, the engine page has been removed from the tab control and made into it's own vi that I want to put on the FPGA target (as its only input and no interaction) but I want to be able to call the engine vi from the main program and not interrupt the main program if I am controlling the pump but just want to see what the engine and pressures are doing.
I added a screen of some of the code tied to the picture above.
Attachments:
virun.jpg ‏226 KB
Untitled2.png ‏148 KB

[fpga] How to view an integrated IP in Modelsim?

Hi,
i integrate a simple adder in my FPGA vi, and i use modelsim to simulate it.
But, i'm wonder how to see my IP in the simulator in order to debug it, because i cannot find it.
Thanks

Hi Mhed !
In order to start in good conditions maybe it would be interesting to use the document below :
Cycle-Accurate Co-Simulation with Mentor Graphics ModelSim
This document explains how to use ModelSim and LabVIEW FPGA from creation, configuration to build. Thanks to it, you'll be able to check you didn't forget a step of configuration or something.
Be also aware of the version you're using : Versions Required
Hope it will help.
Regards,
Antonin G. Associated LabVIEW Developper
National Instruments France
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Communauté francophone des développeurs LabVIEW et des enseignants en STI2D
Si vous souhaitez partage...

Upgrading computer with FPGA interface

We are going to be upgrading a computer that is about 10 years old and uses a Com port to interface to an FPGA, running Lab View. The new computer only has USB, just wondering if a cable converter (with driver) work ok with the new computer runing the old executable? Also wondering if anyone knows if upgrading from windows ME to windows XP will cause any problems? The Lab View also interfaces with an NI PCI-DIO32 card.
Thanks Paul.

Hi GerdW,
Thank you.
it works with your solution, but it create another problem with another vi (see picture).
Regards,
SASA
Attachments:
synamic-simple-Interface-problem.jpg ‏47 KB

Device drive of lab view fpga 2013 for Spartan 3E FPGA

Hi NI
I has get labview 2013
but I need FPGA device drive of Spartan 3E
can NI release it for us !!!!!!!!!!!!
best regards
hi ?Q>

T-REX$ wrote:
Hey mangood,
There currently is no support for the Spartan3E board in LabVIEW FPGA 2013, and I am not aware of any plan for developing support in the near future. Sorry for the bad news...
DEAR
i have lab view 2012 and it has device drvie for spartan FPGA
only one year
may be can NI do this its simple
thank
hi ?Q>

I need any IN LAB View FPGA Engineer,I'm tired of searching

Dear
I have work on vhdl language for more than 2 year on xilinx FPGA using xilinx ISE
I now work on labview FPGA due to its fast programming
I have main problem with LABVIEW FPGA and not solved until know which it as follow
when I need to build system in FPGA in xilinx ISE their a single clock and depend on this clock I will synchroniz the adder and multiplier and other elements using vhdl code so depend on my code this clock will have maximum frequency value and during simulation their is an single clock I can see the change.
But when I work on LAB VIEW FPGA no single clock appear and many clock source appear
for example
in compilation result you can see two clock
And in xlinx log you can see two clock
And from this http://www.ni.com/white-paper/12942/en
you can see three source
please expain to us what is happen !!!!
best regads
hi ?Q>

dear
i take the vi it from here
http://www.ni.com/white-paper/12942/en
please itract me
hi ?Q>

CRIO and ni 9234 modules not working or communicating through fpga with accelerometers, fpga connected to real time application which is also connected to shared variables linked to modbus slave

Hi,
I have a compact rio which has a 4 way chassis attached to that chassis is three ni9234 modules they are linked using fpga to a real time application then using shared variables in the low speed loop that are linked to a modbus slave to communicate with dcs, the ni 9234's have accelerometers connected to them with iepe ac coupled option on the c modules, my problem is the real time application seems to be running okay even when power loss occurs it restarts with no problem and the fpga writes to the portable hard drive bin files fine but without a accelerometer connected I get low noise readings as soon as I connect a accelerometer to any one of the 10 outputs it just goes to a fixed number (0.03125) as soon as disconnect it again it reverts back to reading noise, I have run a scan on the modules and only get a spike when I connect or disconnect the accelerometer, I have tested the voltage at the pins of the module and I get 22 volts dc which makes it more likely that the hardware is not the problem but a software is maybe causing this to hang-up, I attach project and files for your perusal. I also carried out a new project which in scan mode directly linked the module input to shared variable and the same scenerio again. Help would be much appretiated.
Many thanks
Jason
Solved!
Go to Solution.
Attachments:
logger 2plusmodbus2.zip ‏679 KB

Whren using waveform acquisition with the 9234s we recommend the following FPGA and RT template.
http://sine.ni.com/nips/cds/view/p/lang/en/nid/209114
it can be extended as a data logger with:
http://zone.ni.com/devzone/cda/epd/p/id/6388
or using shared variables combined with scan engine
http://zone.ni.com/devzone/cda/tut/p/id/9851
The FPGA in all of these, as well as the RT framework have been used successfully by 1000s of users. I would recommend giving these a try.
Preston Johnson
Principal Sales Engineer
Condition Monitoring Systems
Vibration Analyst III - www.vibinst.org, www.mobiusinstitute.com
National Instruments
[email protected]
www.ni.com/mcm
www.ni.com/soundandvibration
www.ni.com/biganalogdata
512-683-5444

DC to DC converter basics using Labview on FPGA Control with VHDL

DC to DC converter basics using Labview
I am fairly a novice, that is why simplifications required, before I begin thanks in advancefor them who will response
I am designing a DC to DC (Intermediate Bus Converter, a step down BUCK converter, of 24 v input and output 9 v and 5 amp current output), using FPGA controller, I need to program this using VHDL, for which I take LabVIEW, but as I am new so do not have any idea as what are the steps that I need to take for implementation, what types of function that FPGA does in this so that it can generate 24 v and what other mechanisms that have to control inside or outside of FPGA programming and designing that it can give the desired output voltage, if you have any idea about this then I would be glad to receive the steps that are necessary to complete this

NI supports two Spartan 3E products through either LabVIEW FPGA or MultiSIM, the Digital Electronics FPGA Board (http://sine.ni.com/nips/cds/view/p/lang/en/nid/207010) and, if you are in academia, the Xilinx Spartan 3E XUP starter board (as linked by Dennis_Knutson).
Also note that if you wanted to implement some logic in VHDL and have access to that logic in a LVFPGA diagram, you could utilize the Component-level IP (CLIP) fuctionality (http://zone.ni.com/reference/en-XX/help/371599G-01/lvfpgaconcepts/using_component_ip/)

Labview fpga development board

hi all
can i programme my own development board having xillinx fpga using labview fpga .. or lab view fpga can only be used by national instruments hardware ?
Regards

Just to reiterate what was already said, The LabVIEW FPGA generates VHDL code that can not be used or downloaded into non-NI hardware, even if it uses the same Xilinx FPGA.
That being said, there is one board that you can use that is not National Instruments, Xilinx SPARTAN-3E XUP Starter Kit
Regards,
Andrew Eddleman
National Instruments
RIO Embedded Hardware PSE
CompactRIO Developers Guide

Rt / how can a fpga-bitfile be exchanged without recompile the rtexe?

Hello to all,
maybe someone of you knows the trick:
my program have two parts, one is running on RT-OS (LabView RT/PharLap) the other part is on a FPGA. For programming I'm using LV 8.5.1.
In the VI (on RT) which calls the FPGA, is a static path-reference on the bitfile. Idea of this was that the bitfile is dynamically loaded by every start of the RT and when there are bugfixes to do in the FPGA-code, then this could be done with an simple exchange of the bitfile (which I can send to the customer and he replaces then byself the file per FTP).
In fact replacing of the bitfile does not have any effect, it seems that the bitfile is integrated in the RTexe and so cannot be exchanged on harddisk. Only way to replace the bitfile seems to recompile the RTexe with the new bitfile.
Does anyone knows how this can be solved? Or is there no way to do so that a bitfile is loaded at runtime (as a file and not integrated in RTexe)?
Or is this maybe because the VI which calls the bitfile, is forced to be part of the compiled RTexe (build options)?
Greets,
Lars

Hi Lars,
as far as I know there are 2 ways to dynamically download a bitfile to an FPGA
device.
1. Using the NI-RIO driver (available at: http://joule.ni.com/nidu/cds/view/p/id/993/lang/en)
When you install the NI-RIO driver, the RIO Device Setup utility is installed,
which allows you to download bitfiles to the flash memory of your FPGA device.
After that when the device is reset or powerup, the device itself can load and
start this new bitfile. Just make sure that the option "Autoload VI on
device powerup" or "Autoload VI on device reboot" is set
accordingly under Device Settings in the RIO Device Setup utility. Change
these options of the device so that the bitfile is loaded on a reset or power
loss, then reset or cycle the power for the device.
2. Using the FPGA Target System Replication utility as discussed under: http://zone.ni.com/devzone/cda/tut/p/id/6465
With the help of the VIs included in this utility (http://digital.ni.com/public.nsf/websearch/AF4FF0C65AF31B4348257337006A144A?OpenDocument) you can basically set the same options and select a bitfile similar to the RIO
Device Setup utility of the NIO-RIO driver. Similar to the RIO Device Setup
utility you can download your bitfile to the flash memory of your FPGA and then
reset or power cycle your device.
I hope this information helps you.
Best regards,
Balazs

Problem modifying FPGA code in an Application Builder-based system

I've inherited a working test system which uses LabVIEW FPGA, LabVIEW, Application Builder, and third party tools. The FPGA module (a FlexRIO) is responsible for generating test signals to a DUT and acquiring DUT output data. The host LabVIEW code controls the FlexRIO and acquires the test data. Application Builder is used to convert the host LabVIEW code to a Windows DLL so that it can be in turn controlled by higher level data analysis software running on Windows.
All of this currently works, and we're using it on a daily basis to test production devices.
We need to modify the FPGA operation to change the way the tests operate. We've modified the the FPGA VI to operate as we need it to and rebuilt the FPGA code (resulting in a new bit file), but subsequent runs of the test stack do not show the change to the operation of the FPGA code (the signals it is generating look exactly the same as in the original, unmodified, VI). We've tried renaming, deleting, and moving the bit file, but operation of the system is always exactly the same, even when the bit file is named differently or not located in the expected directory. We can't seem to affect the behavior we get out of the FPGA. It seems like we're not rebuilding something correctly, or that the system somehow has a copy of the old bit file stored away some place that it's using instead of the desired bit file.
We've verified that the newly created bit file is different than the original bit file, so it appears that the FPGA build process is succeeeding. I see no errors from LabVIEW when I build the FPGA code.
Does a DLL-ized version of LabVIEW host code operate the same as the same VI run from within the LabVIEW environment? When the DLL loads the FlexRIO, does it do so from the same referenced file path (I have the "Open FPGA VI Reference" properties set to use the bitfile, and the "Run the FPGA VI" checkbox is checked). We've power-cycled the host PXIe chassis between software runs to make sure the configuration memory in the FlexRIO is cleared.
It seems highly suspicious that we see the FPGA come up and run even when the bit file has been renamed or moved from the directory indicated in the "Open FPGA VI Reference". I would think that the DLL would attempt to open that file, fail to find it, and trip some sort of error dialog. But this doesn't occur, the FPGA gets loaded normally, and the test system operates as if nothing had been touched.
Previous developers were able to make this build process work, but it seems we're missing some critical step needed to actually update the code that ends up running on the FPGA.
The system is LabVIEW 2012.

The FPGA build definition has the bitfile filename hardwired into it, so the name is constant across rebuilds of the FPGA code. So we always have the same bitfile name (and consequently if we're not careful about saving the old files, then the old bitfile will be overwritten by a new build).
I could try your suggestion about the alternate calling method, but I'm hesitant about changing a build process that was known to work. It seems to me that I'm somehow not building the software correctly, as if I don't understand something about the DLL build process that's keeping the new FPGA code from being used.
To reiterate, our build process is:
1) Modify the LabVIEW FPGA VI
2) "Run" the FPGA VI to compile it (by the way, last night we tried a "Rebuild" on the FPGA code from the right click menu off the VI in the LabVIEW project and that also has failed to change the results)
3) Build the host DLL code by right clicking the DLL build definition in the LabVIEW project and selecting Build
4) Copy the resulting host DLL over to the directory location where the higher level Windows software expects to find it
5) Run the higher level Windows software (at which point we view waveforms generated by the FlexRIO to see if the FPGA's behavior has changed).
We've verified that the LabVIEW DLL won't rebuild if we rename the bitfile (LabVIEW gives an error saying it can't find the bitfile). We've also verified that the higher level Windows software won't run if the LabVIEW DLL is renamed in its directory (so we know that that exact copy is being opened by the Windows software). Yet we can't seem to modify the FlexRIO's behavior through this process.

Error with target resource of the FPGA in project tree

Good evening
I am completing the tutorial about NIeval quit of CompactRIO.
I am using a RIO 9631 and after compiling the 1st example(simple counter example)
I get this error:
"you cannot run this VI because the because the target resource does not match the actual type of device"
I go to project and I see than FPGA resouerce is RIO0, the same that is by default in the project, the same is in the tutorial guide and the same appears in MAX.
I have to say I had installed the Labview before testing the card so I only have copied the folder of the tutorials in my desktop and I have opened from there.
Can u help to solve this error??

Hi,
Ok here is some update on the issue:
After again querying the WF table
we found that this is the WF which ran
"PA Mass Assignment Transaction Workflow" (PARMATRX) 5109937 -10001.
Also the notification went to a person who is not at all related to this project in any way. Want to find out how to over the come with the problem of blue dots and need to find how the submitter attribute value in the WF is getting populated.
Please let me know your views/hints.
Thanks
Anand.

Simulations in FPGA

Hi all,
I started learning LabVIEW FPGA very recently and I have a query regarding the simulations that can be done. I don't have any NI FPGA hardware with me. I am using only the development computer for programming in LabVIEW FPGA.
I am using "Execute VI on»Development Computer with Simulated I/O"option when I add only FPGA in my project to simulate some simple codes. But when I try to add Real Time system and then add FPGA, I/O ports never get listed under FPGA. I am attaching a snapshot of Course Manual of LabVIEW FPGA and project file I tried to replicate from the same. You can see that there are no I/O ports listed in my project file.
How to get these ports appear in my project file without posessing any Hardware? ( I have replicated the steps given to simulate CompactRIO or Single-Board RIO in http://digital.ni.com/public.nsf/allkb/F466AD83D24F041D8625714900709583 , but when I added a program and compiled it, it gave error after it couldn't find the real time target).
If I am able to add the ports, is it possible for me to get the simulated waveforms from those ports like I can view waveforms using ModelSim? Is it not possible to create a complete project and check the input and output waveforms in simulator on the development computer itself without having any of the hardware?
Kindly help me out. Thanks in advance.
Sharath

Well, what you're asking for is a very common request, and I definitely agree that being able to see waveforms from within LabVIEW would be extremely useful.
It is really straight-forward to use ModelSIM, as you mentioned, or even ISIM (ships with the LabVIEW FPGA Module Compilation Tools) to get simulated waveforms.
ISIM can get a little difficult if you need to simulate the host interface, as this requires VHDL knowledge to write a test-bench. Fortunately, there is a really easy way to work around needing to write VHDL to provide the diagram with data. My usual method is shown here:
Using a conditional disable structure like this lets you pre-load a memory block with IO data. You can even use an initialization VI to load in TDMS or CSV data if you want. (the default case just has my IO item)
If you do have access to ModelSIM PE, Cycle Accurate Co-Simulation is a really powerful tool, and I highly recommend it. It's probably less tedious than you think once you get used to it.
Cycle accurate simulation is currently only supported on some targets, and unfortunately not the 9074 that you appear to be using. For simulation, I would recommend adding an RSeries(784x or 785x) or FlexRIO device to the project to simulate small pieces of code.
Cheers!
TJ G

Virtex6:Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings

Hello，everyone.
I am using virtex6 FPGA and trying to download mcs file to PROM and have failed.
I download .bit file to FPGA and succeed.
When i try to download .mcs file to PROM XCF128X-FTG64C(BPI Flash) and choose Slave SelectMAP Mode
and the process is about 68% it fails.
The message below the IMapct is as belows:
done.
PROGRESS_END - End Operation.
Elapsed time =      0 sec.
// *** BATCH CMD : identifyMPM
// *** BATCH CMD : assignFile -p 1 -file "C:/Users/Administrator/Desktop/TEST/LED/led.bit"
'1': Loading file 'C:/Users/Administrator/Desktop/TEST/LED/led.bit' ...
done.
INFO:iMPACT:2257 - Startup Clock has been changed to 'JtagClk' in the bitstream stored in memory,
but the original bitstream file remains unchanged.
UserID read from the bitstream file = 0xFFFFFFFF.
INFO:iMPACT:501 - '1': Added Device xc6vlx240t successfully.
INFO:iMPACT - Current time: 2014/3/13 8:48:14
// *** BATCH CMD : Program -p 1
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
INFO:iMPACT - 1: Over-temperature condition detected! [ 230.52C > 120.00C]
1: Device Temperature: Current Reading: 230.52 C, Max. Reading: 230.52 C
1: VCCINT Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
1: VCCAUX Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
'1': Programming device...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 0111 1110 0100 1011 1100 0000
INFO:iMPACT:579 - '1': Completed downloading bit file to device.
INFO:iMPACT:188 - '1': Programming completed successfully.
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
INFO:iMPACT - '1': Checking done pin....done.
'1': Programmed successfully.
PROGRESS_END - End Operation.
Elapsed time =     23 sec.
Selected part: XCF128X
// *** BATCH CMD : attachflash -position 1 -bpi "XCF128X"
// *** BATCH CMD : assignfiletoattachedflash -position 1 -file "C:/Users/Administrator/Desktop/TEST/LED/leda.mcs"
INFO:iMPACT - Current time: 2014/3/13 8:49:32
// *** BATCH CMD : Program -p 1 -dataWidth 16 -rs1 NONE -rs0 NONE -bpionly -e -v -loadfpga
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 66000000.
Validating chain...
Boundary-scan chain validated successfully.
INFO:iMPACT - 1: Over-temperature condition detected! [ 230.52C > 120.00C]
1: Device Temperature: Current Reading: 230.52 C, Max. Reading: 230.52 C
1: VCCINT Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
1: VCCAUX Supply: Current Reading:   2.997 V, Max. Reading:   2.997 V
'1': BPI access core not detected. BPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file D:/Xilinx/14.3/ISE_DS/ISE/virtex6/data/xc6vlx240t_jbpi.cor.
'1': Downloading core...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 0111 1110 0100 1011 1100 0000
INFO:iMPACT:2492 - '1': Completed downloading core to device.
Current cable speed is set to 6.000 Mhz.
Cable speed is default to 3Mhz or lower for BPI operations.
Current cable speed is set to 3.000 Mhz.
Setting Flash Control Pins ...
Setting Configuration Register ...
Populating BPI common flash interface ...
Common Flash Interface Information Query completed successfully.
INFO:iMPACT - Common Flash Interface Information from Device:
INFO:iMPACT - Verification string: 51 52 59
INFO:iMPACT - Manufacturer ID:        49
INFO:iMPACT - Vendor ID:             01
INFO:iMPACT - Device Code:           18
Setting Flash Control Pins ...
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
'1': Erasing device...
'1': Start address = 0x00000000, End address = 0x008CE03B.
done.
'1': Erasure completed successfully.
Setting Flash Control Pins ...
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
INFO:iMPACT - Using Word Programming.
'1': Programming Flash.
done.
Setting Flash Control Pins ...
'1': Flash Programming completed successfully.
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
'1': Reading device contents...
done.
'1': Verification completed.
Setting Flash Control Pins ...
Current cable speed is resumed to 6.000 Mhz.
'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
`Elapsed time =    814 sec.
and i find many people have met the same thing. But they are spartan series FPGA and i try to low the Resistances of Mode pins,M0 M1 and M2, but the problem does not been solved.
I have read the status Registers and find there is an over-temperature state
and in Impact i could not readback the registers. It is strange.
I am anxious about this problem and have not solved it yet
What reasons may it be?
Hope for your answer, thank you

Hi~I want to know if you solve the configuration problem for virtex-6?
As I encounter the  same configuration problem, I want to consult  you with some question.
Can I have your email?
gszakacs wrote:
I have measured the VCCINT and find it is 1.0V, not 2.997V;
That is not at all surprising. I always assumed the problem is with reading the XADC (system monitor) block and not with the voltage or temperature.
my Reference board is ML605
That would have been nice to know at the beginning...
It seems that you have selected the correct mode, assuming your jumpers are set as required in the ML605 Hardware User's Guide. See table 1-27, table 1-33 and the note below it about switch S1.
I'm not that familiar with the details of this reference design, but it may be that the slave SelectMap circuitry requires a reset or power cycle to actually configure the FPGA. Have you tried power-cycling to see if the FPGA boots from the flash?
I'd also suggest that you select the V6 in the JTAG chain view, then go to the debug menu of Impact and select Read Device Status (this is from memory, but it's something like that). That will not only show the bits of the configuration status register, but also describe what each bit means. Among other things you can check the state of the FPGA's configuration logic and the Mode pins.

Lab view programming to control the printer

Hi,
As part of my senior design, I am working on LAb view programming. Though I know some basics of lab view, I don't know how to apporach it in the right way. Our device is a dispenser (ink jet printer) which has to dispense user defined amount in user defined location. lab view program has to be interfaced with the printer to do so. I know some basics of lab view and currently I don't know where I am heading to. I have also read the one discussion forum on Lab view FPGA to control an inkjet printer which discussed about FPGA module.
Thanks,
Sundeep

No, I'm saying that depending on the level that you are interfacing would determine whether the FPGA would be a good answer. If you are interfacing to an existing inkjet printer, where you may need to just provide it with the appropriate values through an existing interface, then FPGA would probably not be the answer. If you are connecting at a lower hardware level where you need to directly control the print head, positioning "stuff" etc., then it might. But as I said, and you have reiterated, it is expensive. FPGA allows you to through "software" define a hardware logic. It is particularly good for those things that need very critical timings between signals as it basically programs a digital logic card, therefore the timings are no longer software/operating system dependent, they are in hardware, with outputs and internal signal changes dependent on internal, hardware, clock transistions. You mention that the printer is an epson inkjet. Are you talking a standard, plug it into a computer, epson printer? Are you expecting to "hack" its hardware to get control of those functions you mentioned, like user controlled ink quantity, etc.? You will have to tell us what you have in a little more detail, and what you expect to have to do. Interface to a printer can be hooking up a parallel, or usb connection and sending the codes to print (which in LabVIEW can be its own hurdle!) to the extreme of cutting into existing hardware to introduce "internal" control signals that substitute for the original. The first step to trying to solve your technical problem is being able to describe what it is that you are trying to do, in as much detail as possible.
Putnam
Certified LabVIEW Developer
Senior Test Engineer
Currently using LV 6.1-LabVIEW 2012, RT8.5
LabVIEW Champion

Fpga I/O viewer

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