FPGA_syn

Hi,
I want to download open sparc T1 on ML 505 ,my plan is to run the diags and later to run the c programs ,
For this what all the points I have to take care while synthesising because I saw in DV guide that in $DV_ROOT/design /sys/iop/include/xst_defines.h there are options to set without spu,8 TLB etc...
I changed those things and kept only FPGA_SYN because I want the full core regression .will a single thread option will serve my purpose?
while buillding the vcs model I didn't give any FPGA option is this ok?
Now I am using rxil -device=xc5vlx -all with the modification in include file as i said above ?please give me your suggestions
Thanks in advance

Hello,
Note that if you remove all options except FPGA_SYN, the resulting core might be too big to fit on the ML505-V5LX110T. The other options are used to remove logic to fit the core into a smaller FPGA.
Also, while it's fine to run sims with no arguments, It would also be beneficial to run with the exact compiler defines you are using for synthesis. This just verifies that there are no logical problems with the set of compiler defines you are using.
formalGuy

Similar Messages

  • Trying to run in FPGA mode with VCS Diag fails

    I am trying to run OpenSparc with vcs in FPGA mode. The command I used is
    sims -sim_type=vcs -group=thread1_mini -novera_build -novera_run -max_cycle= 50000 -config_rtl=FPGA_SYN -config_rtl=FPGA_SYN_NO_SPU -config_rtl=FPGA_SYN_1THREAD
    The Diag I used is bypass_win.s The status.log shows it failed
    When I remove FPGA option the diag pass.
    Can anyone please let me know which diag I should use in FPGA mode.
    I wanted to remove latches so I use FPGA_SYN. Also, is it necessary to run FPGA using script rsynp.
    Can I synthesize the design other than Simplicity.
    Thanks
    Upendra

    Hi Durgam,
    Thanks for quick reply. I use these options but sim fails at compile time
    [upendra@dev2 sim]$ sims -sim_type=vcsi -group=thread1_mini -novera_build -novera_run -max_cycle=50000 -vcs_build_args=FPGA_SYN -vcs_build_args=FPGA_SYN_NO_SPU -vcs_build_args=FPGA_SYN_1THREAD
    sims -sim_type=vcsi -group=thread1_mini -novera_build -novera_run -max_cycle=50000 -vcs_build_args=FPGA_SYN -vcs_build_args=FPGA_SYN_NO_SPU -vcs_build_args=FPGA_SYN_1THREAD
    sims: ================================================
    sims: Simulation Script for OpenSPARC T1
    sims: Copyright (c) 2001-2006 Sun Microsystems, Inc.
    sims: All rights reserved.
    sims: ================================================
    sims: start_time Tue Nov 25 15:03:26 PST 2008
    sims: running on dev2.liga.local
    sims: uname is Linux dev2.liga.local 2.6.9-11.ELsmp #1 SMP Wed Jun 8 17:54:20 CDT 2005 i686 i686 i386 GNU/Linux
    sims: version 1.262
    sims: dv_root /pub/upendra2/t1_1.6/sim
    sims: model_dir /pub/upendra2/t1_1.6/sim/OpenSPARC_model
    sims: tre_search /pub/upendra2/t1_1.6/sim/2008_11_25_1/tre/sims.iver
    sims: Frozen tre_search /pub/upendra2/t1_1.6/sim/tools/env/tools.iver
    sims: processing diaglist /pub/upendra2/t1_1.6/sim/verif/diag/master_diaglist () ..
    sims: processing group thread1_mini
    sims: using config file /pub/upendra2/t1_1.6/sim/tools/src/sims/sims.config ()
    sims -nosimslog -sim_build -novera_build -sys=core1 -vcs_rel_name=thread1_mini_2008_11_25_1 -novera_run -max_cycle=50000 -vcs_build_args=FPGA_SYN -vcs_build_args=FPGA_SYN_NO_SPU -vcs_build_args=FPGA_SYN_1THREAD -nosas -novcs_run
    sims: ================================================
    sims: Simulation Script for OpenSPARC T1
    sims: Copyright (c) 2001-2006 Sun Microsystems, Inc.
    sims: All rights reserved.
    sims: ================================================
    sims: start_time Tue Nov 25 15:03:27 PST 2008
    sims: running on dev2.liga.local
    sims: uname is Linux dev2.liga.local 2.6.9-11.ELsmp #1 SMP Wed Jun 8 17:54:20 CDT 2005 i686 i686 i386 GNU/Linux
    sims: version 1.262
    sims: dv_root /pub/upendra2/t1_1.6/sim
    sims: model_dir /pub/upendra2/t1_1.6/sim/OpenSPARC_model
    sims: tre_search /pub/upendra2/t1_1.6/sim/2008_11_25_1/tre/sims.iver
    sims: using config file /pub/upendra2/t1_1.6/sim/tools/src/sims/sims.config ()
    sims: using random seed 3932776618
    sims: creating model directory /pub/upendra2/t1_1.6/sim/OpenSPARC_model/core1/thread1_mini_2008_11_25_1
    sims: setenv VERA_LIBDIR /pub/upendra2/t1_1.6/sim/OpenSPARC_model/core1/thread1_mini_2008_11_25_1/vera
    sims: LM_LICENSE_FILE : /apps/mentor/modeltech/license.dat
    sims: Building rtl model
    sims: Caught a SIGDIE. sim_build_cmd not defined at /pub/upendra2/t1_1.6/sim/tools/src/sims/sims,1.262 line 2456.
    sims: Caught a SIGDIE. Could not build model for regression at /pub/upendra2/t1_1.6/sim/tools/src/sims/sims,1.262 line 1281.
    I looked at DVGuide. In section 5.3 "Additional FPGA Support in OpenSPARC T1" section It talks about +define. then I serch sims script & found -rtl_config option which I previously used. But with this option the diag fails.
    What should I use in order to compile & run successfully. Pl. let me know.
    Thanks,
    Upendra

  • About OpenSPARCT1.1.4 simulation

    Hi,
    We have tried running regression of OpenSPARCT1.1.4 with follow command:
    sims -sim_type=ncv -group=thread1_mini -novera_build -novera_run
    It runs correctly. But when we check the file $pwd/2007_05_29/config.v,
    there is no any information like `define FPGA_SYN_NO_SPU
    `define FPGA_SYN_1THREAD
    `define FPGA_SYN
    Can we believe it runs in the thread1_mini envirement instead of core1 envirement?
    shall we write like this:
    sims -sim_type=ncv -group=thread1_mini -novera_build -novera_run -config_rtl="FPGA_SYN_NO_SPU" -config_rtl="FPGA_SYN_1THREAD" -config_rtl="FPGA_SYN" ?
    Who can help us ? Thanks!

    Responses below ..
    Hi,
    We have tried running regression of OpenSPARCT1.1.4
    with follow command:
    sims -sim_type=ncv -group=thread1_mini
    -novera_build -novera_run
    It runs correctly. But when we check the file
    $pwd/2007_05_29/config.v,
    there is no any information like `define
    FPGA_SYN_NO_SPU
    define FPGA_SYN_1THREAD
    define FPGA_SYN
    Can we believe it runs in the thread1_mini
    envirement instead of core1 envirement?Above will build full core1 model but run only single thread diags on that model.
    >
    shall we write like this:
    sims -sim_type=ncv -group=thread1_mini
    -novera_build -novera_run
    -config_rtl="FPGA_SYN_NO_SPU"
    -config_rtl="FPGA_SYN_1THREAD"
    -config_rtl="FPGA_SYN" ?Yes, this is the way to build single thread model specifically for FPGAs. Notice that these three flags are orthogonal. In other words, FPGA_SYN_1THREAD creates single thread model. FPGA_SYN_NO_SPU removes SPU from the model and FPGA_SYN is primarily to replace custom implementation for some logic with FPGA synthesizable code. If you are targeting FPGA technology, and are concerned about the size of the design, then enabling all three flags gives the lowest possible area.
    Also note that the correct syntax of the sims command is -
    sims -sim_type=ncv -group=thread1_mini -novera_build -novera_run -vcs_build_args=+define+FPGA_SYN -vcs_build_args=+define+FPGA_SYN_1THREAD -vcs_build_args=+define+FPGA_SYN_NO_SPU
    Thanks.
    Who can help us ? Thanks!

  • Manually synthesizing the T1 core

    In the OpenSPARC T1 1.6 release, scripts are included to automatically synthesize T1 blocks. The synthesis can be done by Synplicity or by XST. The scripts to do this are named rsynp and rxil, respectively. The usage of these scripts is documented in the OpenSPARC T1 Design and Verification Guide.
    These scripts are written in Shell language and Perl, so they will probably not run on a Windows machine unless a package of Unix utilities is installed. Such packages do exist, and some are free to download.
    However, if you want to manually compile the design using ISE, for example, there are a few things to keep in mind. First of all, the original code had blocks which are not synthesizable. For example all the RAM models are not synthesizable. To make them synthesizable for FPGA, and to get them to map into Block RAM, we added several compile options into the code. When settting up a compile to ISE, the required option is to set the FPGA_SYN . This makes all the changes necessary for FPGA synthesis, including selecting RAM models that will map correctly into Xilinx block RAM. (Anyone who wants to map to Altera or other FPGA brands may need to modify the models a little bit). I don't know exactly how to select these compile options, but it's probably a command similar to "+define+FPGA_SYN+".
    The above command will enable FPGA synthesis, but there are other options available to reduce the size of the core (see the Design and Verification Guide). For example the FPGA_SYN_1THREAD reduces the size of the core by reducing it from 4 threads to 1. This is required if you are synthesizing into a smaller FPGA like the XC4VFX50 found on the ML410 board. Other options allow for even more reduction in size.
    Another problem encountered with Windows machines is the memory limitation. Windows XP machines are only able to address 3GB of physical memory, and the Virtual memory is limited to 2GB. If any process requires more than 2GB, it won't be able to complete. We ran into this exact problem when running place & route. Even though we put 4GB of RAM in the machine, it still ran out of memory (the Virtual memory was the limit). See the following web site for a possible workaround.
    http://www.xilinx.com/support/answers/14932.htm
    formalGuy

    Here is a little more information on how to synthesize the T1 core manually from the ISE GUI. This is the procedure to follow if you can't use our automated scripts rsynp and rxil. (For exampe if you are on a Windows machine).
    From the start menu, select ISE -> Project Navigator
    From the Project Navigator GUI, select File->New Project ( the new project wizard may come up automatically if it is the first time you are running Project Navigator
    Select a project name and the project path
    Click next
    The next window is Device Properties:
    Select the correct Device, Package, and speed grade for your board.
    Click next
    The next window is Create new source.
    Just skip this and click next
    The next window is Add existing Source
    Just skip this and click next
    Finish the Wizard to create the project.
    Now search for the following file which is a source list for the sparc core:
    design/sys/iop/sparc/xst/sparc.flist
    You need to select add sources and add each file from the file list to the project.
    (There should just be some way to add the list, but I cannot figure out how to do it. Any ISE experts out there?)
    Note that you may need to copy files ending with .behV to a new name ending with .v so that ISE recognizes the files a Verilog files.
    The next step is to set the compile time macros: To do this:
    1. Look for the ISE sub-window on the left labeled "Processes"
    2. Find the "Synthesize-XST" entry in that window
    3. Right click on that entry and select "Properties"
    4. In the popup window "Process Properties - Synthesis Options,
    select "synthesis options in the left window
    5. Set the property display level to "Advanced"
    6. In the right list scroll down to find the property
    "Verilog Macros"
    7. Type the value FPGA_SYN FPGA_SYN_1THREAD FPGA_SYN_NO_SPU FPGA_SYN_8TLB in that box.
    Finally Run synthesis:
    From the Processes window, right-click on Synthesize-XST and select Run in the popup Menu.
    Hopefully, this gives enough details that you can figure the rest out.
    formalGuy

  • OpenSPARC T1 & T2 questions

    Does anybody know the complete gates counts of OS T1 & T2 when synthesized for ASIC
    implementations?
    Regards,
    Hatzimiltos

    Hi Hatzimiltos,
    I have only numbers for the T1 core (Not the whole T1) on FPGAs.
    The T1 core requires the following Virtex-5 resources
    Lookup-tables (LUT) 52000
    Block RAM 115
    For these numbers, the core was compiled with the following options:
    FPGA_SYN -- Uses FPGA-synthesizable RAM models, and other FPGA optimizations
    FPGA_SYN_NO_SPU -- Does not include the SPU
    FPGA_SYN_16TLB -- Reduces the ITLB and DTLB from 64 entries to 16. Because the TLBs are fully associative, they are implemented with a CAM, which is not efficiently implemented in FPGAs. Therefore, reducing the size results in a significant savings in LUTs.
    formalGuy

  • Obp stops at "Powering on Opensparc T1"

    Dear all,
    I try to boot 1c4t OpenSolaris from a sparc core synthesized in XST and integrated into the EDK project provided by the Design and Verification kit. However, OBP stuck at "Powering on OpenSparc T1" forever.
    To run synthesis, I directly invoke xst (instead of use rxil) in the $DV_ROOT/design/sys/iop/sparc/xst directory:
    xst -ifn XC5VLX110.xst
    Here are some modifications I made before running xst synthesis:
    -bufr is not a valid option for virtex 5 devices, so I removed it.
    As I read from Xilinx data sheet, the device on XUPV505 should be packaged by ff1136 instead of ff1153, so I made the change accordingly:
    -p xc5vlx110-ff1153-3 to -p xc5vlx110t-ff1136-3
    And as suggested by the DV User Guide, FPGA_SYN is defined and FPGA_SYN_1THREAD is removed since I intend to synthesize a sparc core with 4 thread pipeline.
    Any problem with the OpenSolaris and OBP image is ruled out, since if the FPGA is configured with the bitstream from the out-of-box SysACE, but the DDR memory is overwritten by downloading images via XMD, OpenSolaris booted normally. Anybody has the same problem? Is there any potential problem with the options in XST synthesis or XPS flow? I am wondering if the problem is only related to XST, and if synthesized with Synplicity, the design can boot Solaris normally.
    Any help is appreciated. Thanks!
    -Jin
    Edited by: jouyang on Jan 27, 2009 2:14 PM
    Edited by: jouyang on Jan 27, 2009 2:15 PM
    Edited by: jouyang on Jan 27, 2009 5:44 PM

    Hi Jin,
    This will probably be a very complicated debugging problem. Here goes!
    1. First, examine all the synthesis logs created by XST for any kind of warning or error. Then, examine the EDK place and route logs, and especially the timing reports for any timing violation, or other kind of error.
    2. Next, I suggest running a stand-alone tests on the processor. The procedure to do this is found in the OpenSPARC T1 Design and Verification User's Guide. Start by running the core1_mini regression. All tests should pass. If so, then run core1_full. This will take a while (approx 700 tests at 30 seconds per test).
    3. If all the above tests pass, then examine the software. There are four different boot PROM images, depending on whether you have a 1-thread or a 4-thread core, and whether you want to boot Solaris, or just run a program on top of Hypervisor. If you are booting a 4-thread core, the proper file should be 1c4t_obp_prom.bin Also, double-check that you are loading the prom.bin and the OpenSolaris image to the correct locations.
    Good Luck!
    formalGuy

Maybe you are looking for